TimeQuest Timing Analyzer report for atari800core
Sun Jun 29 12:46:00 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. TimeQuest Timing Analyzer Summary
  3. Parallel Compilation
  4. SDC File List
  5. Clocks
  6. Slow 1200mV 85C Model Fmax Summary
  7. Timing Closure Recommendations
  8. Slow 1200mV 85C Model Setup Summary
  9. Slow 1200mV 85C Model Hold Summary
 10. Slow 1200mV 85C Model Recovery Summary
 11. Slow 1200mV 85C Model Removal Summary
 12. Slow 1200mV 85C Model Minimum Pulse Width Summary
 13. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 14. Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 15. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 16. Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 17. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 18. Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 19. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 20. Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 21. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 22. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 23. Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 24. Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'
 25. Setup Times
 26. Hold Times
 27. Clock to Output Times
 28. Minimum Clock to Output Times
 29. Output Enable Times
 30. Minimum Output Enable Times
 31. Output Disable Times
 32. Minimum Output Disable Times
 33. Slow 1200mV 85C Model Metastability Report
 34. Slow 1200mV 0C Model Fmax Summary
 35. Slow 1200mV 0C Model Setup Summary
 36. Slow 1200mV 0C Model Hold Summary
 37. Slow 1200mV 0C Model Recovery Summary
 38. Slow 1200mV 0C Model Removal Summary
 39. Slow 1200mV 0C Model Minimum Pulse Width Summary
 40. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 41. Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 42. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 43. Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 44. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 45. Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 46. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 47. Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 48. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 49. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 50. Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 51. Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 52. Setup Times
 53. Hold Times
 54. Clock to Output Times
 55. Minimum Clock to Output Times
 56. Output Enable Times
 57. Minimum Output Enable Times
 58. Output Disable Times
 59. Minimum Output Disable Times
 60. Slow 1200mV 0C Model Metastability Report
 61. Fast 1200mV 0C Model Setup Summary
 62. Fast 1200mV 0C Model Hold Summary
 63. Fast 1200mV 0C Model Recovery Summary
 64. Fast 1200mV 0C Model Removal Summary
 65. Fast 1200mV 0C Model Minimum Pulse Width Summary
 66. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 67. Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 68. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 69. Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 70. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 71. Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 72. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 73. Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 74. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'
 75. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'
 76. Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'
 77. Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'
 78. Setup Times
 79. Hold Times
 80. Clock to Output Times
 81. Minimum Clock to Output Times
 82. Output Enable Times
 83. Minimum Output Enable Times
 84. Output Disable Times
 85. Minimum Output Disable Times
 86. Fast 1200mV 0C Model Metastability Report
 87. Multicorner Timing Analysis Summary
 88. Setup Times
 89. Hold Times
 90. Clock to Output Times
 91. Minimum Clock to Output Times
 92. Board Trace Model Assignments
 93. Input Transition Times
 94. Slow Corner Signal Integrity Metrics
 95. Fast Corner Signal Integrity Metrics
 96. Setup Transfers
 97. Hold Transfers
 98. Recovery Transfers
 99. Removal Transfers
100. Report TCCS
101. Report RSKM
102. Unconstrained Paths
103. TimeQuest Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2013 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+----------------------------------------------------------------------------------------+
; TimeQuest Timing Analyzer Summary                                                      ;
+--------------------+-------------------------------------------------------------------+
; Quartus II Version ; Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition ;
; Revision Name      ; atari800core                                                      ;
; Device Family      ; Cyclone III                                                       ;
; Device Name        ; EP3C16E144C8                                                      ;
; Timing Models      ; Final                                                             ;
; Delay Model        ; Combined                                                          ;
; Rise/Fall Delays   ; Enabled                                                           ;
+--------------------+-------------------------------------------------------------------+


+------------------------------------------+
; Parallel Compilation                     ;
+----------------------------+-------------+
; Processors                 ; Number      ;
+----------------------------+-------------+
; Number detected on machine ; 4           ;
; Maximum allowed            ; 2           ;
;                            ;             ;
; Average used               ; 1.29        ;
; Maximum used               ; 2           ;
;                            ;             ;
; Usage by Processor         ; % Time Used ;
;     Processor 1            ; 100.0%      ;
;     Processor 2            ;  29.4%      ;
;     Processors 3-4         ;   0.0%      ;
+----------------------------+-------------+


+------------------------------------------------------+
; SDC File List                                        ;
+------------------+--------+--------------------------+
; SDC File Path    ; Status ; Read at                  ;
+------------------+--------+--------------------------+
; atari800core.sdc ; OK     ; Sun Jun 29 12:45:44 2014 ;
+------------------+--------+--------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clocks                                                                                                                                                                                                                                                                                                                                                                                                                                                                                 ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; Clock Name                                                                     ; Type      ; Period  ; Frequency ; Rise  ; Fall    ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master                                                                        ; Source                                                                           ; Targets                                                                            ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Generated ; 11.640  ; 85.91 MHz ; 0.000 ; 5.820   ; 50.00      ; 1         ; 3           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 1         ; 1           ;       ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ; Generated ; 11.640  ; 85.91 MHz ; 7.482 ; 13.302  ; 50.00      ; 1         ; 3           ; 231.4 ;        ;           ;            ; false    ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0] ; { \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] } ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; Generated ; 34.920  ; 28.64 MHz ; 0.000 ; 17.460  ; 50.00      ; 11        ; 63          ;       ;        ;           ;            ; false    ; FPGA_CLK                                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]  ; { \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] }  ;
; FPGA_CLK                                                                       ; Base      ; 200.000 ; 5.0 MHz   ; 0.000 ; 100.000 ;            ;           ;             ;       ;        ;           ;            ;          ;                                                                               ;                                                                                  ; { FPGA_CLK }                                                                       ;
+--------------------------------------------------------------------------------+-----------+---------+-----------+-------+---------+------------+-----------+-------------+-------+--------+-----------+------------+----------+-------------------------------------------------------------------------------+----------------------------------------------------------------------------------+------------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Fmax Summary                                                                                   ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; 45.95 MHz  ; 45.95 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 127.75 MHz ; 127.75 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


----------------------------------
; Timing Closure Recommendations ;
----------------------------------
HTML report is unavailable in plain text report export.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup Summary                                                                    ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.853 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.790 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold Summary                                                                     ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.453 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.454 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery Summary                                                                 ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 5.551 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.532 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal Summary                                                                  ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.716 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.661 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width Summary                                                       ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.517  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.153 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.423 ; 0.000         ;
; FPGA_CLK                                                                       ; 99.862 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.853 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 10.449     ;
; 0.902 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.221     ; 10.388     ;
; 0.974 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 10.301     ;
; 1.015 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.221     ; 10.275     ;
; 1.017 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 10.270     ;
; 1.078 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 10.197     ;
; 1.087 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 10.188     ;
; 1.094 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.202     ; 10.215     ;
; 1.132 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 10.155     ;
; 1.137 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 10.158     ;
; 1.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 10.139     ;
; 1.170 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.205     ; 10.136     ;
; 1.191 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 10.084     ;
; 1.204 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 10.097     ;
; 1.216 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 10.064     ;
; 1.217 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 10.084     ;
; 1.224 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.221     ; 10.066     ;
; 1.234 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.209     ; 10.068     ;
; 1.241 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 10.046     ;
; 1.258 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 10.036     ;
; 1.263 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 10.026     ;
; 1.263 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.205     ; 10.043     ;
; 1.279 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.221     ; 10.011     ;
; 1.296 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.979      ;
; 1.301 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.974      ;
; 1.306 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 9.981      ;
; 1.310 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.221     ; 9.980      ;
; 1.320 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.960      ;
; 1.334 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.957      ;
; 1.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.920      ;
; 1.362 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.221     ; 9.928      ;
; 1.365 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.929      ;
; 1.386 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.903      ;
; 1.392 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.902      ;
; 1.400 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.875      ;
; 1.408 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.881      ;
; 1.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.865      ;
; 1.410 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 9.877      ;
; 1.427 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.864      ;
; 1.434 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.841      ;
; 1.437 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.203     ; 9.871      ;
; 1.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.844      ;
; 1.447 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 9.848      ;
; 1.452 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.205     ; 9.854      ;
; 1.455 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.820      ;
; 1.458 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.203     ; 9.850      ;
; 1.459 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.816      ;
; 1.472 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.817      ;
; 1.482 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.812      ;
; 1.482 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 9.819      ;
; 1.501 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.793      ;
; 1.505 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 9.790      ;
; 1.519 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.786      ;
; 1.524 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.767      ;
; 1.525 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.755      ;
; 1.531 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.758      ;
; 1.534 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.771      ;
; 1.538 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.737      ;
; 1.551 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.740      ;
; 1.556 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.724      ;
; 1.558 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.733      ;
; 1.559 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.716      ;
; 1.571 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 9.724      ;
; 1.575 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.205     ; 9.731      ;
; 1.584 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.696      ;
; 1.596 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.693      ;
; 1.610 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.679      ;
; 1.620 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.655      ;
; 1.627 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.678      ;
; 1.628 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.663      ;
; 1.631 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.658      ;
; 1.633 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 9.654      ;
; 1.643 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.646      ;
; 1.645 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.207     ; 9.659      ;
; 1.646 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.210     ; 9.655      ;
; 1.651 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.640      ;
; 1.660 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.620      ;
; 1.667 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.608      ;
; 1.674 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.615      ;
; 1.677 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.628      ;
; 1.682 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.598      ;
; 1.688 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.592      ;
; 1.698 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.577      ;
; 1.700 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.605      ;
; 1.703 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.602      ;
; 1.732 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.562      ;
; 1.739 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.552      ;
; 1.745 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.223     ; 9.543      ;
; 1.760 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.534      ;
; 1.761 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.236     ; 9.514      ;
; 1.767 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.522      ;
; 1.783 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 9.512      ;
; 1.786 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.494      ;
; 1.799 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.501      ;
; 1.809 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.222     ; 9.480      ;
; 1.811 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.483      ;
; 1.835 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.231     ; 9.445      ;
; 1.851 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.220     ; 9.440      ;
; 1.858 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.217     ; 9.436      ;
; 1.858 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.223     ; 9.430      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                              ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.790 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 8.663      ;
; 2.897 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.554      ;
; 2.967 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.484      ;
; 2.972 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.479      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.005 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.217     ; 8.419      ;
; 3.023 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.428      ;
; 3.123 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 8.315      ;
; 3.138 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.303      ;
; 3.140 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 8.298      ;
; 3.140 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 8.298      ;
; 3.140 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 8.298      ;
; 3.140 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 8.298      ;
; 3.187 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 8.244      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.204 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 8.221      ;
; 3.236 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.215      ;
; 3.255 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 8.209      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.261 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.212     ; 8.168      ;
; 3.272 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.179      ;
; 3.277 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.174      ;
; 3.286 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.165      ;
; 3.303 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 8.150      ;
; 3.304 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.137      ;
; 3.311 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 8.153      ;
; 3.317 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 8.147      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.320 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 8.110      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.373 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.225     ; 8.043      ;
; 3.392 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 8.061      ;
; 3.402 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.039      ;
; 3.404 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 8.047      ;
; 3.404 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 8.037      ;
; 3.465 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.963      ;
; 3.470 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.177     ; 7.994      ;
; 3.472 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 7.964      ;
; 3.503 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.938      ;
; 3.503 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.938      ;
; 3.505 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 7.946      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.509 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 7.929      ;
; 3.512 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 7.939      ;
; 3.518 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.923      ;
; 3.523 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.918      ;
; 3.588 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.223     ; 7.830      ;
; 3.593 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.860      ;
; 3.596 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 7.840      ;
; 3.619 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.188     ; 7.834      ;
; 3.621 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.820      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[0]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[1]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[2]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[3]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[4]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[5]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[6]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.633 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot_counter_reg[7]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 7.795      ;
; 3.655 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 7.770      ;
; 3.680 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 7.771      ;
; 3.699 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.183     ; 7.759      ;
; 3.717 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.190     ; 7.734      ;
; 3.729 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 7.712      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                           ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                ; To Node                                                                                                                                  ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[7]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[7]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[4]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[4]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[5]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[5]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[6]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[6]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_valid_reg[3]                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_valid_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                        ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.453 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.081      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[2]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[2]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                          ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreIndirect ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cyclePreRead     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.080      ; 0.746      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                  ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                  ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.454 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.454 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.746      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 0.746      ;
; 0.466 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.758      ;
; 0.509 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 0.801      ;
; 0.704 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.126      ;
; 0.715 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.007      ;
; 0.732 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.024      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.736 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.028      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.739 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.031      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.740 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.032      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.741 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.033      ;
; 0.744 ; ram_bena_reg[0]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.036      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.036      ;
; 0.745 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.037      ;
; 0.749 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.041      ;
; 0.750 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.042      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.758 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.050      ;
; 0.766 ; seq_reg[0]                                                                                                      ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.058      ;
; 0.802 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.094      ;
; 0.809 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.101      ;
; 0.814 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.106      ;
; 0.833 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.125      ;
; 0.848 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.140      ;
; 0.853 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.145      ;
; 0.855 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.147      ;
; 0.856 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.148      ;
; 0.869 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.161      ;
; 0.908 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.200      ;
; 0.932 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.224      ;
; 0.938 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_psel_dly[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.230      ;
; 0.941 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.233      ;
; 0.963 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.255      ;
; 0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.385      ;
; 0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.385      ;
; 0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.385      ;
; 0.963 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.385      ;
; 0.965 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.387      ;
; 0.965 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.387      ;
; 0.965 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.387      ;
; 0.972 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.394      ;
; 0.973 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.395      ;
; 0.976 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg          ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 1.389      ;
; 0.978 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.400      ;
; 0.982 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.274      ;
; 1.016 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.308      ;
; 1.022 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.314      ;
; 1.026 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.078      ; 1.316      ;
; 1.062 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]  ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.484      ;
; 1.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11] ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.503      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.383      ;
; 1.091 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.383      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.385      ;
; 1.093 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.385      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.392      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.101 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.393      ;
; 1.102 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.394      ;
; 1.107 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 1.518      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.109 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.401      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.110 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.402      ;
; 1.111 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.403      ;
; 1.129 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.551      ;
; 1.133 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]  ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.555      ;
; 1.150 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 1.561      ;
; 1.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.190      ; 1.587      ;
; 1.187 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.479      ;
; 1.190 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.482      ;
; 1.202 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.494      ;
; 1.206 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.498      ;
; 1.212 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.504      ;
; 1.222 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.514      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.224 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.516      ;
; 1.231 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.523      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.233 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.525      ;
; 1.240 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.532      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.533      ;
; 1.241 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.533      ;
; 1.242 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.080      ; 1.534      ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                     ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 5.551 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.912      ;
; 5.551 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 5.912      ;
; 5.586 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.180     ; 5.875      ;
; 5.586 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.180     ; 5.875      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.438      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 5.431      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.428      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.428      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.438      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.428      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.428      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.438      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.193     ; 5.438      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.428      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.428      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 5.431      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 5.431      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.200     ; 5.431      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 5.421      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 5.421      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[3]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|enabled_out_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.420      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[10]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[12]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[8]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 5.421      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.010 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|memory_ready_reg                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.194     ; 5.437      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 5.420      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 5.420      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.223     ; 5.407      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.223     ; 5.407      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 5.414      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.215     ; 5.415      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.210     ; 5.420      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.427      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.204     ; 5.426      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.419      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.419      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.207     ; 5.423      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.207     ; 5.423      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 5.431      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.224     ; 5.406      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.209     ; 5.421      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.207     ; 5.423      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.207     ; 5.423      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[17]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.207     ; 5.423      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.419      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 5.414      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.427      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.214     ; 5.416      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 5.414      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.216     ; 5.414      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.214     ; 5.416      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[8]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.214     ; 5.416      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[9]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.214     ; 5.416      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[9]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.214     ; 5.416      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.427      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.203     ; 5.427      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[11]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[10]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.231     ; 5.399      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.211     ; 5.419      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[14]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[15]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[14]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.214     ; 5.416      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[0]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[1]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[4]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[5]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[3]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[2]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[7]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[6]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.213     ; 5.417      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[7]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.205     ; 5.425      ;
; 6.011 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.224     ; 5.406      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                         ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.389     ; 3.578      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 3.590      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.375     ; 3.592      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.375     ; 3.592      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.367     ; 3.600      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 3.590      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.367     ; 3.600      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.375     ; 3.592      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.377     ; 3.590      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.375     ; 3.592      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.391     ; 3.576      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.379     ; 3.588      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.367     ; 3.600      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.393     ; 3.574      ;
; 7.532 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.389     ; 3.578      ;
; 7.533 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.387     ; 3.579      ;
; 7.540 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.191     ; 3.780      ;
; 7.540 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.779      ;
; 7.540 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.779      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 3.764      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 3.764      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 3.764      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 3.764      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 3.778      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.777      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 3.777      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.204     ; 3.766      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 3.764      ;
; 7.541 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 3.764      ;
; 7.548 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.248     ; 3.715      ;
; 7.548 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.248     ; 3.715      ;
; 7.548 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.248     ; 3.715      ;
; 7.551 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.720      ;
; 7.551 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.720      ;
; 7.551 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.720      ;
; 7.553 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.262     ; 3.696      ;
; 7.553 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.248     ; 3.710      ;
; 7.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.266     ; 3.690      ;
; 7.555 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.264     ; 3.692      ;
; 7.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.262     ; 3.693      ;
; 7.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.260     ; 3.695      ;
; 7.556 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.252     ; 3.703      ;
; 7.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 3.704      ;
; 7.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 3.704      ;
; 7.557 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.250     ; 3.704      ;
; 7.558 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 3.886      ;
; 7.558 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 3.886      ;
; 7.558 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 3.886      ;
; 7.558 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 3.886      ;
; 7.558 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 3.886      ;
; 7.558 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 3.886      ;
; 7.641 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.819      ;
; 7.641 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.819      ;
; 7.791 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.204     ; 3.516      ;
; 7.791 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.204     ; 3.516      ;
; 7.791 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.204     ; 3.516      ;
; 7.791 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.204     ; 3.516      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.384      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.175     ; 3.381      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.379      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.379      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.379      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.379      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.379      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.379      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.379      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.370      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.375      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.375      ;
; 8.085 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 3.375      ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                       ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.143      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.148      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.144      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.144      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.144      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.144      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.144      ;
; 2.716 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.196      ; 3.144      ;
; 2.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.134      ;
; 2.717 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.185      ; 3.134      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.718 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.145      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.206      ; 3.157      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.204      ; 3.155      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.719 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.209      ; 3.160      ;
; 2.724 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.151      ;
; 2.724 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.151      ;
; 2.724 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.151      ;
; 2.724 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.151      ;
; 2.724 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.151      ;
; 2.724 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.195      ; 3.151      ;
; 2.725 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.141      ;
; 2.725 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.141      ;
; 2.725 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.141      ;
; 2.725 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.141      ;
; 2.725 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.184      ; 3.141      ;
; 2.952 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 3.278      ;
; 2.952 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 3.279      ;
; 2.952 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 3.279      ;
; 2.952 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.180      ; 3.278      ;
; 3.115 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.547      ;
; 3.115 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.200      ; 3.547      ;
; 3.207 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.183      ; 3.622      ;
; 3.207 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.183      ; 3.622      ;
; 3.207 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.183      ; 3.622      ;
; 3.207 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.183      ; 3.622      ;
; 3.207 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.183      ; 3.622      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                        ;
+-------+---------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                     ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.661 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.696      ; 5.589      ;
; 4.661 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.696      ; 5.589      ;
; 4.704 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.207      ; 5.143      ;
; 4.704 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 5.138      ;
; 4.704 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.202      ; 5.138      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.198      ; 5.147      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 5.144      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 5.144      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.142      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.143      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 5.144      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.143      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.193      ; 5.142      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.143      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.143      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.143      ;
; 4.717 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.194      ; 5.143      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.137      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 5.147      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.137      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.137      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.137      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 5.147      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 5.136      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.186      ; 5.136      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.137      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.197      ; 5.147      ;
; 4.718 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.137      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.139      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.139      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.139      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.139      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.139      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.147      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.147      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.201      ; 5.152      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.196      ; 5.147      ;
; 4.719 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.195      ; 5.146      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 5.137      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 5.137      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 5.137      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.140      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.140      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.139      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.140      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.185      ; 5.137      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.139      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.140      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.139      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.139      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.140      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.188      ; 5.140      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.139      ;
; 4.720 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.187      ; 5.139      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 5.124      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 5.123      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 5.123      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 5.124      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 5.124      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 5.124      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 5.123      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 5.124      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 5.123      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 5.123      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.170      ; 5.123      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 5.124      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 5.124      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 5.125      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.173      ; 5.126      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[0]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[1]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[2]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[3]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[4]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[5]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[6]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[7]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
; 4.721 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[8]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 5.127      ;
+-------+---------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                        ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.517 ; 5.737        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.518 ; 5.738        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.520 ; 5.740        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.521 ; 5.741        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.522 ; 5.742        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.526 ; 5.746        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.527 ; 5.747        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.527 ; 5.747        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.527 ; 5.747        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.527 ; 5.747        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.527 ; 5.747        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.527 ; 5.747        ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.605 ; 5.763        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.605 ; 5.763        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.605 ; 5.763        ; 0.158          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                   ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.153 ; 17.373       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                      ;
; 17.153 ; 17.373       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                                 ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[5]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[6]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Creg                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|Vreg                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[4]                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[0]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[2]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[3]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[5]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[6]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf3_reg[7]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[5]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|keyboard_overrun_reg                                                ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[3]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[4]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[5]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[6]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[7]                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[4]                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[5]                                                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_ip_framing_reg                                               ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_ip_overrun_reg                                               ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[1]                                              ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[2]                                              ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[3]                                              ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|sio_in_reg                                                          ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[0]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[1]                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|synchronizer:sio_in1_synchronizer|ff_reg[0]                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|synchronizer:sio_in1_synchronizer|ff_reg[1]                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|synchronizer:sio_in1_synchronizer|ff_reg[2]                         ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_keyboard_scanner:pokey_keyboard_scanner1|keycode_latch_reg[0] ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serial_ip_framing_reg                                               ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serial_ip_overrun_reg                                               ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[1]                                                                                                      ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[29]                                                                                                     ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[4]                                                                                                      ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[5]                                                                                                      ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[1]                                                                                                      ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[4]                                                                                                      ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[5]                                                                                                      ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[2]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[4]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[5]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[6]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audf1_reg[7]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                                                          ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                                                          ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                                                                ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                                                                ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                                                                ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqen_reg[1]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[0]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[2]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                                                           ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[1]                               ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer1|delay_line:underflow0_delay|shift_reg[2]                               ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0]                               ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_reg                                                                                    ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[3]                                                                                        ;
; 17.158 ; 17.378       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[16]                                                                                                         ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                          ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                          ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                          ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[0]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[1]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[2]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[3]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[4]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[5]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[6]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc0_reg[7]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[0]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[1]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[2]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[3]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[4]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[5]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[6]                                                        ;
; 17.159 ; 17.379       ; 0.220          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audc2_reg[7]                                                        ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                   ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.423 ; 17.423       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.435 ; 17.435       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.484 ; 17.484       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.496 ; 17.496       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 85C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                        ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.862  ; 99.862       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.929  ; 99.929       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.070 ; 100.070      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.137 ; 100.137      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                                ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 6.382 ; 6.899 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.055 ; 4.268 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.415 ; 4.619 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.455 ; 4.694 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.594 ; 4.844 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 6.382 ; 6.899 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.192 ; 6.643 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.964 ; 4.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.446 ; 4.681 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.783 ; 5.002 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.651 ; 4.862 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.192 ; 6.643 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 7.323 ; 7.640 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.343 ; 6.575 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.946 ; 4.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -2.016 ; -2.123 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -2.045 ; -2.152 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -2.042 ; -2.149 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -2.039 ; -2.146 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -2.050 ; -2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -2.036 ; -2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -2.040 ; -2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -2.018 ; -2.125 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -2.028 ; -2.135 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.941 ; -3.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.941 ; -3.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -3.323 ; -3.513 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -3.361 ; -3.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.464 ; -3.672 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -3.328 ; -3.543 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.805 ; -2.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.805 ; -2.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -3.352 ; -3.572 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -3.679 ; -3.881 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -3.552 ; -3.748 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.991 ; -3.176 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -6.125 ; -6.432 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -5.173 ; -5.383 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.875 ; -3.069 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                        ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.389  ; 3.932  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.289  ; 3.000  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.279  ; 2.990  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.284  ; 2.995  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.293  ; 3.004  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.302  ; 3.013  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.389  ; 3.932  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.303  ; 3.014  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.313  ; 3.024  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.289  ; 3.000  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.376  ; 3.919  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.290  ; 3.001  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.376  ; 3.919  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.388  ; 3.931  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.300  ; 3.011  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.450  ; 3.995  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.588  ; 3.277  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.588  ; 3.277  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.588  ; 3.277  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.430  ; 3.975  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.425  ; 3.970  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.356  ; 2.151  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.477  ; 3.180  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.486  ; 3.189  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.608  ; 3.297  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.450  ; 3.995  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.616  ; 3.305  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.616  ; 3.305  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.606  ; 3.295  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.442  ; 3.987  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.586  ; 3.275  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.596  ; 3.285  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.900  ; 5.139  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 4.900  ; 5.139  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.535  ; 3.796  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.300  ; 3.011  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.311  ; 3.022  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.378  ; 6.693  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.944  ; 3.858  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 5.015  ; 4.685  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.182  ; 7.408  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.666  ; 3.791  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 11.350 ; 11.342 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 8.773  ; 8.650  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 10.994 ; 11.171 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.349  ; 9.152  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.350 ; 11.342 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 10.605 ; 10.837 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 10.605 ; 10.837 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 8.516  ; 8.221  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.285  ; 8.078  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 7.146  ; 6.853  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 6.795  ; 6.551  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 8.743  ; 8.440  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.743  ; 8.437  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 8.687  ; 8.440  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 7.763  ; 7.530  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.335  ; 8.082  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.284  ; 2.160  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.933  ;        ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 8.693  ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.417 ; 2.133 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.422 ; 2.138 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.431 ; 2.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.440 ; 2.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.573 ; 3.117 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.441 ; 2.157 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.451 ; 2.167 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.427 ; 2.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.429 ; 2.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.560 ; 3.104 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.572 ; 3.116 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.725 ; 2.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.725 ; 2.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.725 ; 2.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.616 ; 3.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.612 ; 3.158 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.542 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.615 ; 2.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.623 ; 2.332 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.745 ; 2.440 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.636 ; 3.182 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.753 ; 2.448 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.753 ; 2.448 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.743 ; 2.438 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.628 ; 3.174 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.723 ; 2.418 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.733 ; 2.428 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.664 ; 2.920 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.973 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.664 ; 2.920 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.439 ; 2.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.449 ; 2.165 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 5.521 ; 5.838 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.080 ; 2.997 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.096 ; 3.775 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.286 ; 6.516 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.797 ; 2.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 4.293 ; 4.127 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 4.293 ; 4.166 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 6.697 ; 6.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.336 ; 4.127 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 7.632 ; 7.711 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 3.807 ; 3.417 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 6.589 ; 6.752 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.222 ; 3.931 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 4.255 ; 3.945 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 3.807 ; 3.417 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 5.670 ; 5.445 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 3.634 ; 3.448 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 4.366 ; 4.061 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 3.634 ; 3.448 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 3.755 ; 3.474 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 3.928 ; 3.686 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.468 ; 1.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.163 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.927 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.512 ; 3.512 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.512 ; 3.512 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.512 ; 3.512 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.512 ; 3.512 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.869 ; 3.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.281 ; 4.281 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.313 ; 4.313 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.705 ; 4.705 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.693 ; 4.693 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 5.073 ; 5.073 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.692 ; 4.692 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.300 ; 4.300 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.300 ; 4.300 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.290 ; 4.290 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.285 ; 4.285 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.275 ; 4.275 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.285 ; 4.285 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.543 ; 4.159 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.148 ; 2.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.148 ; 2.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.148 ; 2.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.148 ; 2.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.492 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.887 ; 2.916 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.918 ; 2.947 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.295 ; 3.324 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.283 ; 3.312 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.648 ; 3.677 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.282 ; 3.311 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.906 ; 2.935 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.906 ; 2.935 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.896 ; 2.925 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.891 ; 2.920 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.881 ; 2.910 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.891 ; 2.920 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.546 ; 3.178 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.158     ; 3.398     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.158     ; 3.398     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.158     ; 3.398     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.158     ; 3.398     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.504     ; 3.744     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.895     ; 4.135     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.926     ; 4.166     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.295     ; 4.535     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.282     ; 4.522     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.619     ; 4.859     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.267     ; 4.507     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.895     ; 4.135     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.895     ; 4.135     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.885     ; 4.125     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.895     ; 4.135     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.885     ; 4.125     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.895     ; 4.135     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.020     ; 4.404     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.039     ; 2.039     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.039     ; 2.039     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.039     ; 2.039     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.039     ; 2.039     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.372     ; 2.372     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.748     ; 2.748     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.777     ; 2.777     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.131     ; 3.131     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.119     ; 3.119     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.443     ; 3.443     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.105     ; 3.105     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.748     ; 2.748     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.748     ; 2.748     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.738     ; 2.738     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.747     ; 2.747     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.737     ; 2.737     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.747     ; 2.747     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.044     ; 3.412     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


----------------------------------------------
; Slow 1200mV 85C Model Metastability Report ;
----------------------------------------------
No synchronizer chains to report.


+----------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Fmax Summary                                                                                    ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; Fmax       ; Restricted Fmax ; Clock Name                                                                     ; Note ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
; 48.53 MHz  ; 48.53 MHz       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;      ;
; 133.99 MHz ; 133.99 MHz      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;      ;
+------------+-----------------+--------------------------------------------------------------------------------+------+
This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods.  FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock.  Paths of different clocks, including generated clocks, are ignored.  For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup Summary                                                                     ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.524 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3.214 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold Summary                                                                      ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.402 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.403 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery Summary                                                                  ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 6.080 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 7.871 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 2.430 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 4.223 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.518  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.114 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.426 ; 0.000         ;
; FPGA_CLK                                                                       ; 99.837 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.524 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 9.795      ;
; 1.538 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.767      ;
; 1.574 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.758      ;
; 1.591 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 9.728      ;
; 1.605 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.700      ;
; 1.615 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.703      ;
; 1.632 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.673      ;
; 1.699 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.606      ;
; 1.745 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 9.572      ;
; 1.745 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 9.579      ;
; 1.745 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.573      ;
; 1.754 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.179     ; 9.583      ;
; 1.759 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.551      ;
; 1.768 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 9.555      ;
; 1.778 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.554      ;
; 1.786 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 9.533      ;
; 1.792 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.526      ;
; 1.800 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.505      ;
; 1.808 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 9.523      ;
; 1.809 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 9.510      ;
; 1.812 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 9.505      ;
; 1.823 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.482      ;
; 1.853 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.457      ;
; 1.861 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.457      ;
; 1.862 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 9.461      ;
; 1.886 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.432      ;
; 1.894 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.411      ;
; 1.912 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 9.422      ;
; 1.915 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 9.404      ;
; 1.917 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.388      ;
; 1.929 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.376      ;
; 1.931 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 9.399      ;
; 1.953 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.367      ;
; 1.966 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 9.356      ;
; 1.975 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.181     ; 9.360      ;
; 1.981 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.324      ;
; 1.999 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 9.331      ;
; 2.005 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 9.314      ;
; 2.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 9.310      ;
; 2.014 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 9.320      ;
; 2.023 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.282      ;
; 2.027 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 9.309      ;
; 2.030 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 9.287      ;
; 2.046 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.259      ;
; 2.048 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.257      ;
; 2.055 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.265      ;
; 2.074 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 9.250      ;
; 2.080 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 9.243      ;
; 2.083 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.237      ;
; 2.084 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 9.240      ;
; 2.085 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 9.249      ;
; 2.088 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.222      ;
; 2.098 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.212      ;
; 2.099 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.221      ;
; 2.136 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 9.181      ;
; 2.146 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 9.187      ;
; 2.147 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.171      ;
; 2.151 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.167      ;
; 2.176 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.129      ;
; 2.182 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.128      ;
; 2.185 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.135      ;
; 2.190 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.193     ; 9.133      ;
; 2.192 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.118      ;
; 2.193 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.127      ;
; 2.196 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.136      ;
; 2.199 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.121      ;
; 2.199 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 9.125      ;
; 2.213 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.097      ;
; 2.228 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.082      ;
; 2.239 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.079      ;
; 2.243 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.062      ;
; 2.248 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 9.085      ;
; 2.261 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 9.057      ;
; 2.292 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.013      ;
; 2.292 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 9.013      ;
; 2.295 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 9.027      ;
; 2.301 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.019      ;
; 2.305 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 9.017      ;
; 2.306 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 9.026      ;
; 2.306 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.182     ; 9.028      ;
; 2.307 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.206     ; 9.003      ;
; 2.320 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 9.000      ;
; 2.326 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 8.991      ;
; 2.330 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 8.987      ;
; 2.333 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.985      ;
; 2.348 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 8.985      ;
; 2.355 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.183     ; 8.978      ;
; 2.369 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.950      ;
; 2.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.185     ; 8.960      ;
; 2.372 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.211     ; 8.933      ;
; 2.379 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.939      ;
; 2.397 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.199     ; 8.920      ;
; 2.411 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 8.921      ;
; 2.414 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.196     ; 8.906      ;
; 2.420 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 8.902      ;
; 2.463 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.197     ; 8.856      ;
; 2.480 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 8.844      ;
; 2.490 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.828      ;
; 2.507 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.198     ; 8.811      ;
; 2.516 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 8.814      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                               ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 3.214 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 8.264      ;
; 3.424 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 8.051      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.522 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.192     ; 7.928      ;
; 3.537 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.938      ;
; 3.625 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.841      ;
; 3.634 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.841      ;
; 3.636 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.828      ;
; 3.640 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.835      ;
; 3.654 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.809      ;
; 3.654 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.809      ;
; 3.654 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.809      ;
; 3.654 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 7.809      ;
; 3.663 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.812      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.669 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.782      ;
; 3.671 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 7.815      ;
; 3.676 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.799      ;
; 3.680 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.795      ;
; 3.716 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.740      ;
; 3.729 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 7.757      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.730 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.725      ;
; 3.772 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.703      ;
; 3.789 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 7.689      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 7.653      ;
; 3.803 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 7.683      ;
; 3.842 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.624      ;
; 3.850 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 7.628      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.860 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.199     ; 7.583      ;
; 3.909 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.566      ;
; 3.929 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.537      ;
; 3.954 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.512      ;
; 3.954 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 7.501      ;
; 3.961 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.505      ;
; 3.964 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.181     ; 7.497      ;
; 4.007 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 7.471      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.011 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.178     ; 7.453      ;
; 4.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.449      ;
; 4.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.449      ;
; 4.059 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.407      ;
; 4.063 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.160     ; 7.419      ;
; 4.066 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.162     ; 7.414      ;
; 4.072 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.197     ; 7.373      ;
; 4.079 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.396      ;
; 4.083 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.383      ;
; 4.085 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.390      ;
; 4.086 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.389      ;
; 4.090 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.164     ; 7.388      ;
; 4.096 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 7.355      ;
; 4.104 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.156     ; 7.382      ;
; 4.149 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.168     ; 7.325      ;
; 4.153 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.167     ; 7.322      ;
; 4.165 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.172     ; 7.305      ;
; 4.185 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.281      ;
; 4.196 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 7.276      ;
; 4.196 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 7.276      ;
; 4.212 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.254      ;
; 4.215 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 7.251      ;
; 4.228 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.197     ; 7.217      ;
; 4.237 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.197     ; 7.208      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                    ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                    ; To Node                                                                                                                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|count_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile1|shift_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                   ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CB2_output_reg                                              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|CB2_output_reg                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.402 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.072      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[1]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|colour_clock_count_reg[3]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[2]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|audf3_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[1]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[2]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[3]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[4]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[5]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[6]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[7]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|simple_counter:counter_hpos|value_reg[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|odd_scanline_reg                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile2|shift_reg[6]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|count_reg[1]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|count_reg[1]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[7]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[0]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pl_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pl_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p3pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pl_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig1_reg                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig2_reg                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|trig0_reg                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vscrol_last_enabled_reg                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p1pf_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pf_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m1pl_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pf_reg[1]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.071      ; 0.669      ;
+-------+----------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                  ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.403 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.669      ;
; 0.404 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 0.669      ;
; 0.418 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.684      ;
; 0.479 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.745      ;
; 0.627 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.010      ;
; 0.661 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.928      ;
; 0.676 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 0.943      ;
; 0.683 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.949      ;
; 0.684 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.950      ;
; 0.685 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.951      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.688 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.954      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.689 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.955      ;
; 0.690 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.956      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.691 ; seq_reg[0]                                                                                                      ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.957      ;
; 0.692 ; ram_bena_reg[0]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.692 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.958      ;
; 0.693 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.959      ;
; 0.709 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.975      ;
; 0.710 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.710 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 0.976      ;
; 0.744 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.010      ;
; 0.755 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.021      ;
; 0.761 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.027      ;
; 0.777 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.043      ;
; 0.789 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.055      ;
; 0.794 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.060      ;
; 0.797 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.063      ;
; 0.802 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.068      ;
; 0.816 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.082      ;
; 0.843 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.109      ;
; 0.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.242      ;
; 0.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.242      ;
; 0.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 1.241      ;
; 0.859 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.242      ;
; 0.861 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.244      ;
; 0.861 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.244      ;
; 0.862 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 1.244      ;
; 0.866 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.167      ; 1.248      ;
; 0.867 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.250      ;
; 0.868 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.134      ;
; 0.877 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.144      ;
; 0.877 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.144      ;
; 0.881 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg          ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 1.254      ;
; 0.885 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_psel_dly[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.151      ;
; 0.892 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.275      ;
; 0.914 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.179      ;
; 0.918 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.184      ;
; 0.935 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.201      ;
; 0.946 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]  ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.329      ;
; 0.950 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.216      ;
; 0.965 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11] ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.348      ;
; 1.001 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.384      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.006 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.272      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.007 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.273      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.274      ;
; 1.008 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]  ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.391      ;
; 1.012 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.278      ;
; 1.012 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.278      ;
; 1.013 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.384      ;
; 1.021 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.287      ;
; 1.024 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.290      ;
; 1.025 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.291      ;
; 1.025 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.291      ;
; 1.025 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.291      ;
; 1.035 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 1.418      ;
; 1.060 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.326      ;
; 1.063 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.329      ;
; 1.078 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 1.449      ;
; 1.088 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.355      ;
; 1.091 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.358      ;
; 1.100 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.366      ;
; 1.106 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.372      ;
; 1.106 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.372      ;
; 1.116 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.382      ;
; 1.126 ; seq_reg[10]                                                                                                     ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.070      ; 1.391      ;
; 1.127 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.072      ; 1.394      ;
; 1.128 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.394      ;
; 1.129 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.395      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.396      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.396      ;
; 1.130 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.071      ; 1.396      ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                       ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 6.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 5.405      ;
; 6.080 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.157     ; 5.405      ;
; 6.118 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 5.366      ;
; 6.118 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.158     ; 5.366      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 4.957      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 4.956      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 4.952      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 4.948      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 4.956      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 4.957      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 4.951      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 4.941      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[17]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[6]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[5]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[4]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[3]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[2]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[1]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[0]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 4.957      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.170     ; 4.957      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 4.948      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.179     ; 4.948      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|rx_data[7]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_last_reg                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[4]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[5]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[9]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[8]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[7]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[6]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[5]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[4]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[3]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[2]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[1]                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|twotone_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|sio_out_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[27]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 4.952      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[20]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[15]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 4.956      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.176     ; 4.951      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[0]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[1]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[2]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[3]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[4]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[6]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[7]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 4.941      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 4.941      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 4.941      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serin_bitcount_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 4.941      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 4.952      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.175     ; 4.952      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[7]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[7]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 4.942      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[6]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 4.942      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[14]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 4.956      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.189     ; 4.938      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[3]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.182     ; 4.945      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[3]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.185     ; 4.942      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[11]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 4.956      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 4.956      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|pot_counter_reg[5]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.191     ; 4.936      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|irqst_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.186     ; 4.941      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[13]                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.171     ; 4.956      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[13]                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[9]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[9]                                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.184     ; 4.943      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
; 6.515 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_15_div|count_reg[4]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.187     ; 4.940      ;
+-------+---------------------------------------+----------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                          ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.172     ; 3.473      ;
; 7.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.174     ; 3.471      ;
; 7.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.472      ;
; 7.871 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.173     ; 3.472      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.458      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.458      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.458      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.458      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.174     ; 3.470      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.174     ; 3.470      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 3.460      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.458      ;
; 7.872 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 3.458      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.357     ; 3.269      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.346     ; 3.280      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.344     ; 3.282      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.344     ; 3.282      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.336     ; 3.290      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.346     ; 3.280      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.336     ; 3.290      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.341     ; 3.285      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.346     ; 3.280      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.344     ; 3.282      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.347     ; 3.279      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.336     ; 3.290      ;
; 7.879 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.353     ; 3.273      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.354     ; 3.271      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.358     ; 3.267      ;
; 7.880 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.360     ; 3.265      ;
; 7.905 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.560      ;
; 7.905 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.560      ;
; 7.905 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.560      ;
; 7.905 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.560      ;
; 7.905 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.560      ;
; 7.905 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.177     ; 3.560      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 3.376      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 3.376      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.224     ; 3.376      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.237     ; 3.363      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.233     ; 3.367      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.221     ; 3.379      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.227     ; 3.373      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.384      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.384      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.216     ; 3.384      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.226     ; 3.374      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.226     ; 3.374      ;
; 7.916 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.226     ; 3.374      ;
; 7.917 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.240     ; 3.359      ;
; 7.917 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.238     ; 3.361      ;
; 7.917 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.234     ; 3.365      ;
; 7.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 3.497      ;
; 7.983 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 3.497      ;
; 8.104 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 3.228      ;
; 8.104 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 3.228      ;
; 8.104 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 3.228      ;
; 8.104 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 3.228      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.154     ; 3.091      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.157     ; 3.088      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.158     ; 3.087      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.158     ; 3.087      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.167     ; 3.078      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.158     ; 3.087      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.158     ; 3.087      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.158     ; 3.087      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.158     ; 3.087      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.154     ; 3.091      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.159     ; 3.086      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.165     ; 3.080      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 3.083      ;
; 8.397 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.162     ; 3.083      ;
+-------+------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.814      ;
; 2.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.814      ;
; 2.430 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.814      ;
; 2.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.814      ;
; 2.430 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.814      ;
; 2.430 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.179      ; 2.825      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.823      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.823      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.168      ; 2.814      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.823      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.823      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.823      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.177      ; 2.823      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 2.819      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.170      ; 2.816      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.159      ; 2.805      ;
; 2.431 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.159      ; 2.805      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.823      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.823      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.176      ; 2.823      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.432 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.181      ; 2.828      ;
; 2.433 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.817      ;
; 2.433 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.817      ;
; 2.433 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.817      ;
; 2.433 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.817      ;
; 2.433 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.817      ;
; 2.433 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.169      ; 2.817      ;
; 2.435 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 2.808      ;
; 2.435 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 2.808      ;
; 2.435 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 2.808      ;
; 2.435 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 2.808      ;
; 2.435 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 2.808      ;
; 2.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 2.934      ;
; 2.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 2.934      ;
; 2.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 2.934      ;
; 2.646 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.156      ; 2.934      ;
; 2.779 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 3.167      ;
; 2.779 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.173      ; 3.167      ;
; 2.859 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 3.232      ;
; 2.859 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 3.232      ;
; 2.859 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 3.232      ;
; 2.859 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 3.232      ;
; 2.859 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.158      ; 3.232      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                         ;
+-------+---------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                     ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 4.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.646      ; 5.084      ;
; 4.223 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.646      ; 5.084      ;
; 4.297 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.183      ; 4.695      ;
; 4.297 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.178      ; 4.690      ;
; 4.297 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.178      ; 4.690      ;
; 4.309 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 4.696      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 4.688      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.174      ; 4.699      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.696      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.696      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.696      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 4.688      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 4.688      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 4.688      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.687      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[3]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.162      ; 4.687      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 4.688      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.163      ; 4.688      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.310 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.169      ; 4.694      ;
; 4.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[18]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 4.699      ;
; 4.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.698      ;
; 4.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.698      ;
; 4.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[7]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 4.699      ;
; 4.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.176      ; 4.703      ;
; 4.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.171      ; 4.698      ;
; 4.312 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[23]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.172      ; 4.699      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.689      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.689      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.689      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.149      ; 4.677      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.148      ; 4.676      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.164      ; 4.692      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.148      ; 4.676      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.149      ; 4.677      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.149      ; 4.677      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.149      ; 4.677      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.164      ; 4.692      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.148      ; 4.676      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[17]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[17]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.164      ; 4.692      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.161      ; 4.689      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.164      ; 4.692      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.164      ; 4.692      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.164      ; 4.692      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.149      ; 4.677      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.148      ; 4.676      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.148      ; 4.676      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.148      ; 4.676      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.149      ; 4.677      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.149      ; 4.677      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.150      ; 4.678      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[14]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
; 4.313 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.152      ; 4.680      ;
+-------+---------------------------------------+-------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.518 ; 5.734        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.519 ; 5.735        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.520 ; 5.736        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[9]                                             ;
; 5.521 ; 5.737        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.522 ; 5.738        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[8]                                             ;
; 5.523 ; 5.739        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.523 ; 5.739        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.523 ; 5.739        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.523 ; 5.739        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.523 ; 5.739        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
; 5.621 ; 5.776        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.621 ; 5.776        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.621 ; 5.776        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                   ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                             ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------+
; 17.114 ; 17.330       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                ;
; 17.114 ; 17.330       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                               ;
; 17.158 ; 17.374       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; sdram_reset_ctrl_n_reg                                                                                                             ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                          ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                     ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                        ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|character_reg[5]                              ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[2]                              ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hblank_reg                                    ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[13][3]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[13][7]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[15][1]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[15][2]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[15][3]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[15][5]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[15][6]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[15][7]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[20][5]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[21][2]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[21][5]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][0]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][1]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][2]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][3]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][4]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][5]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][6]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[29][7]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][0]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][1]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][2]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][3]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][4]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][5]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][6]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[33][7]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[35][4]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][0]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][1]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][2]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][3]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][4]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][5]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][6]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[41][7]           ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[6][5]            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[9][2]            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|reg_file:reg_file1|digit_reg[9][3]            ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[10][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[10][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[11][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[11][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[12][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[12][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[12][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[13][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[13][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[13][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[14][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[14][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[14][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[14][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[15][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[15][4] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[15][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[15][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[16][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[16][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[16][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[16][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[17][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[17][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[17][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[17][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[18][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[18][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[18][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[18][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[19][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[19][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[19][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[19][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[1][4]  ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[20][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[20][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[20][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[20][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][0] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[21][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[22][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[22][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[22][5] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[22][6] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[23][2] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[23][3] ;
; 17.159 ; 17.375       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[23][5] ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.426 ; 17.426       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.428 ; 17.428       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.437 ; 17.437       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.482 ; 17.482       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.491 ; 17.491       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.493 ; 17.493       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                         ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.837  ; 99.837       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.888  ; 99.888       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.920  ; 99.920       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.079 ; 100.079      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.112 ; 100.112      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.162 ; 100.162      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                                ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.625 ; 2.732 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.625 ; 2.732 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.625 ; 2.732 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.651 ; 2.758 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.649 ; 2.756 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.645 ; 2.752 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.654 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 2.642 ; 2.749 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.648 ; 2.755 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.627 ; 2.734 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.627 ; 2.734 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.637 ; 2.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 5.627 ; 6.395 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 3.543 ; 3.836 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 3.872 ; 4.184 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 3.924 ; 4.246 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.024 ; 4.401 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 5.627 ; 6.395 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 5.471 ; 6.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.460 ; 3.743 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 3.928 ; 4.219 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.201 ; 4.551 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.074 ; 4.428 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 5.471 ; 6.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 6.500 ; 6.645 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 5.572 ; 5.678 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.445 ; 3.744 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.739 ; -1.847 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.767 ; -1.875 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.765 ; -1.873 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.761 ; -1.869 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.769 ; -1.877 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.757 ; -1.865 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.763 ; -1.871 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.742 ; -1.850 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.752 ; -1.860 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -2.548 ; -2.811 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -2.548 ; -2.811 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -2.901 ; -3.198 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -2.951 ; -3.257 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -3.016 ; -3.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -2.894 ; -3.216 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -2.424 ; -2.682 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -2.424 ; -2.682 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -2.955 ; -3.231 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -3.220 ; -3.554 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -3.098 ; -3.435 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -2.607 ; -2.863 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -5.438 ; -5.582 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -4.536 ; -4.629 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -2.494 ; -2.777 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                        ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317  ; 3.081  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326  ; 3.090  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336  ; 3.100  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346  ; 3.110  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325  ; 3.089  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.617  ; 3.360  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.617  ; 3.360  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.617  ; 3.360  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637  ; 4.189  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633  ; 4.185  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563  ; 2.365  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507  ; 3.264  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519  ; 3.276  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639  ; 3.382  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.644  ; 3.387  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.644  ; 3.387  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.634  ; 3.377  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648  ; 4.200  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614  ; 3.357  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624  ; 3.367  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.789  ; 5.257  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 4.789  ; 5.257  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.576  ; 3.952  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345  ; 3.109  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.559  ; 6.787  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.139  ; 3.924  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 5.164  ; 4.628  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.313  ; 7.410  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.726  ; 3.933  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 11.186 ; 11.083 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 8.767  ; 8.568  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 10.997 ; 11.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.339  ; 9.009  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.186 ; 11.083 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 10.457 ; 10.635 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 10.457 ; 10.635 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 8.453  ; 8.069  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.236  ; 7.818  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 7.219  ; 6.730  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 6.861  ; 6.650  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 8.701  ; 8.326  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.701  ; 8.301  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 8.639  ; 8.326  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 7.719  ; 7.370  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.365  ; 8.015  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.486  ; 2.369  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.222  ;        ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 8.951  ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 2.555 ; 2.323 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 2.559 ; 2.327 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 2.578 ; 2.346 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 2.588 ; 2.356 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 2.565 ; 2.333 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 2.567 ; 2.335 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 3.859 ; 3.410 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 3.871 ; 3.422 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 2.857 ; 2.604 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 2.857 ; 2.604 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 2.857 ; 2.604 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 3.920 ; 3.473 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 3.917 ; 3.470 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.847 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 2.749 ; 2.510 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 2.760 ; 2.521 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 2.880 ; 2.627 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 3.940 ; 3.493 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 2.885 ; 2.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 2.885 ; 2.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 2.875 ; 2.622 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 3.931 ; 3.484 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 2.855 ; 2.602 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 2.865 ; 2.612 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.809 ; 3.176 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 3.972 ; 4.428 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 2.809 ; 3.176 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 2.577 ; 2.345 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 2.587 ; 2.355 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 5.800 ; 6.034 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 3.375 ; 3.167 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 4.344 ; 3.825 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 6.517 ; 6.622 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 2.959 ; 3.162 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 4.407 ; 4.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 4.407 ; 4.209 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 6.876 ; 6.976 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.469 ; 4.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 7.722 ; 7.708 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 4.073 ; 3.487 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 6.700 ; 6.813 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 4.325 ; 3.934 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 4.372 ; 3.965 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 4.073 ; 3.487 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 5.881 ; 5.690 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 3.763 ; 3.523 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 4.448 ; 4.054 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 3.763 ; 3.523 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 3.896 ; 3.557 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 4.087 ; 3.746 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.766 ; 1.650 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.544 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.278 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.316 ; 3.316 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.316 ; 3.316 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.316 ; 3.316 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.316 ; 3.316 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.649 ; 3.649 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 4.033 ; 4.033 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 4.068 ; 4.068 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.440 ; 4.440 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.421 ; 4.421 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.787 ; 4.787 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.428 ; 4.428 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 4.058 ; 4.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 4.058 ; 4.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 4.048 ; 4.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 4.043 ; 4.043 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 4.033 ; 4.033 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 4.043 ; 4.043 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 4.647 ; 4.271 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.258 ; 2.258 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.258 ; 2.258 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.258 ; 2.258 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.258 ; 2.258 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.577 ; 2.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.947 ; 2.947 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.980 ; 2.980 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.337 ; 3.337 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.320 ; 3.320 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.670 ; 3.670 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.325 ; 3.325 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.971 ; 2.971 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.971 ; 2.971 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.961 ; 2.961 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.956 ; 2.956 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.946 ; 2.946 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.956 ; 2.956 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.750 ; 3.389 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.030     ; 3.101     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.030     ; 3.101     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.030     ; 3.101     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.030     ; 3.101     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.353     ; 3.424     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.714     ; 3.785     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.741     ; 3.812     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 4.081     ; 4.152     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 4.071     ; 4.142     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 4.389     ; 4.460     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 4.066     ; 4.137     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.724     ; 3.795     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.724     ; 3.795     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.714     ; 3.785     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.706     ; 3.777     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.696     ; 3.767     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.706     ; 3.777     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.984     ; 4.360     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.051     ; 2.187     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.051     ; 2.187     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.051     ; 2.187     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.051     ; 2.187     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.362     ; 2.498     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.709     ; 2.845     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.734     ; 2.870     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.060     ; 3.196     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.051     ; 3.187     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.357     ; 3.493     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.046     ; 3.182     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.718     ; 2.854     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.718     ; 2.854     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.708     ; 2.844     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.700     ; 2.836     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.690     ; 2.826     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.700     ; 2.836     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.114     ; 3.475     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Slow 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup Summary                                                                     ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 6.959 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7.644 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold Summary                                                                      ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.187 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.187 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery Summary                                                                  ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 8.892 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 9.755 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+--------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal Summary                                                                   ;
+--------------------------------------------------------------------------------+-------+---------------+
; Clock                                                                          ; Slack ; End Point TNS ;
+--------------------------------------------------------------------------------+-------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1.212 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.128 ; 0.000         ;
+--------------------------------------------------------------------------------+-------+---------------+


+---------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width Summary                                                        ;
+--------------------------------------------------------------------------------+--------+---------------+
; Clock                                                                          ; Slack  ; End Point TNS ;
+--------------------------------------------------------------------------------+--------+---------------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 5.605  ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 17.206 ; 0.000         ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; 17.437 ; 0.000         ;
; FPGA_CLK                                                                       ; 99.405 ; 0.000         ;
+--------------------------------------------------------------------------------+--------+---------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                         ; To Node                                      ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 6.959 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.506      ;
; 6.979 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 4.490      ;
; 7.007 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.458      ;
; 7.009 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 4.460      ;
; 7.036 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.424      ;
; 7.046 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.101     ; 4.433      ;
; 7.051 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.409      ;
; 7.056 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.418      ;
; 7.056 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 4.413      ;
; 7.064 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.409      ;
; 7.066 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.394      ;
; 7.067 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.106     ; 4.407      ;
; 7.073 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 4.396      ;
; 7.075 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.390      ;
; 7.081 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.389      ;
; 7.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.391      ;
; 7.081 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.379      ;
; 7.086 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.374      ;
; 7.113 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.347      ;
; 7.116 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.344      ;
; 7.124 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.341      ;
; 7.129 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.341      ;
; 7.130 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.330      ;
; 7.135 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.332      ;
; 7.138 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.325      ;
; 7.140 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 4.329      ;
; 7.141 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.327      ;
; 7.145 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.315      ;
; 7.153 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.307      ;
; 7.153 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.317      ;
; 7.161 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.311      ;
; 7.163 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.297      ;
; 7.165 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.302      ;
; 7.174 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.291      ;
; 7.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 4.297      ;
; 7.180 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.280      ;
; 7.183 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.277      ;
; 7.186 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 4.292      ;
; 7.188 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.275      ;
; 7.189 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.279      ;
; 7.192 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.276      ;
; 7.194 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.115     ; 4.271      ;
; 7.197 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.263      ;
; 7.201 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.259      ;
; 7.202 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 4.275      ;
; 7.205 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 4.272      ;
; 7.208 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.255      ;
; 7.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.248      ;
; 7.212 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.255      ;
; 7.218 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.245      ;
; 7.223 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.249      ;
; 7.226 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.246      ;
; 7.228 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.244      ;
; 7.229 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.238      ;
; 7.234 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 4.238      ;
; 7.237 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.233      ;
; 7.246 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.230      ;
; 7.247 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.213      ;
; 7.250 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.111     ; 4.219      ;
; 7.253 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.215      ;
; 7.257 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.211      ;
; 7.258 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.210      ;
; 7.264 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 4.213      ;
; 7.268 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.195      ;
; 7.269 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.191      ;
; 7.269 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.199      ;
; 7.281 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.187      ;
; 7.285 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.178      ;
; 7.288 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.175      ;
; 7.289 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 4.188      ;
; 7.291 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.177      ;
; 7.291 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.172      ;
; 7.296 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.171      ;
; 7.297 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.109     ; 4.174      ;
; 7.301 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.167      ;
; 7.312 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.156      ;
; 7.314 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.162      ;
; 7.317 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.153      ;
; 7.329 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.139      ;
; 7.335 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.128      ;
; 7.336 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[4]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.139      ;
; 7.341 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.122      ;
; 7.346 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.122      ;
; 7.355 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.108      ;
; 7.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.114     ; 4.108      ;
; 7.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.110      ;
; 7.358 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.118      ;
; 7.361 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.117     ; 4.102      ;
; 7.361 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[4]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.114      ;
; 7.364 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.112      ;
; 7.365 ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.105     ; 4.110      ;
; 7.365 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.107     ; 4.108      ;
; 7.371 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.096      ;
; 7.371 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[5]                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.097      ;
; 7.382 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.112     ; 4.086      ;
; 7.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ; sdram_ctrl:sdram_controller|r_sdram_addr[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 4.086      ;
; 7.384 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ; sdram_ctrl:sdram_controller|r_sdram_addr[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.120     ; 4.076      ;
; 7.386 ; sdram_reset_n_reg                                                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_addr[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.113     ; 4.081      ;
; 7.388 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; sdram_ctrl:sdram_controller|r_sdram_addr[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.114     ; 4.078      ;
; 7.389 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[5]                                              ; sdram_ctrl:sdram_controller|r_sdram_addr[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 4.087      ;
+-------+---------------------------------------------------------------------------------------------------------------------------------------------------+----------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Setup: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                               ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 7.644 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.895      ;
; 7.662 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.877      ;
; 7.724 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.815      ;
; 7.730 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.809      ;
; 7.737 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.802      ;
; 7.756 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.783      ;
; 7.760 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.779      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.763 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.759      ;
; 7.778 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.761      ;
; 7.784 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[0]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 3.744      ;
; 7.803 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.728      ;
; 7.807 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.727      ;
; 7.817 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.714      ;
; 7.817 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.714      ;
; 7.817 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[1]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.714      ;
; 7.817 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.714      ;
; 7.835 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 3.710      ;
; 7.863 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.676      ;
; 7.867 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.672      ;
; 7.869 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.670      ;
; 7.898 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.636      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.924 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer2|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.599      ;
; 7.929 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.605      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.933 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 3.591      ;
; 7.938 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[22]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 3.607      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.946 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer1|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.107     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.953 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer3|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 3.574      ;
; 7.956 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[0]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.578      ;
; 7.968 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[31]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.566      ;
; 7.969 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 3.557      ;
; 7.970 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pot0_reg[4]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.098     ; 3.559      ;
; 7.974 ; ram_do_reg[3]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.560      ;
; 7.981 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 3.564      ;
; 7.985 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.537      ;
; 8.012 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[26]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.522      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[3]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[4]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[5]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[6]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.017 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|count_reg[7]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 3.514      ;
; 8.023 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.516      ;
; 8.025 ; ram_do_reg[1]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[9]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.514      ;
; 8.035 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[4]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.082     ; 3.510      ;
; 8.064 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[7]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.468      ;
; 8.064 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[6]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 3.468      ;
; 8.069 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 3.454      ;
; 8.073 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[36]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 3.461      ;
; 8.077 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[2] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.445      ;
; 8.080 ; ram_do_reg[7]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 3.458      ;
; 8.084 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer2|delay_line:underflow0_delay|shift_reg[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.438      ;
; 8.088 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[35]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.451      ;
; 8.094 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[5]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.445      ;
; 8.095 ; ram_do_reg[2]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.444      ;
; 8.096 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.098     ; 3.433      ;
; 8.106 ; ram_do_reg[0]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.433      ;
; 8.109 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[1]                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.089     ; 3.429      ;
; 8.116 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[37]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.088     ; 3.423      ;
; 8.120 ; ram_do_reg[6]              ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 3.421      ;
; 8.126 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.396      ;
; 8.130 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[0]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.392      ;
; 8.130 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[1]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.392      ;
; 8.130 ; sdram_request_complete_reg ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer3|count_reg[2]                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 3.392      ;
+-------+----------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                                                                                                                   ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                       ; To Node                                                  ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; sdram_request_complete_reg                                                                                      ; sdram_request_complete_reg                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_init_fsm[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|sdram_rdy                                                                           ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_refr_act                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.188 ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1                                                        ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.307      ;
; 0.194 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.314      ;
; 0.198 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.318      ;
; 0.266 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20] ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 0.460      ;
; 0.276 ; seq_reg[5]                                                                                                      ; seq_reg[6]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.395      ;
; 0.284 ; seq_reg[7]                                                                                                      ; seq_reg[8]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.403      ;
; 0.292 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.412      ;
; 0.292 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.411      ;
; 0.293 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.413      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_init_tmr[9]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; seq_reg[0]                                                                                                      ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.294 ; sdram_ctrl:sdram_controller|r_bst_stp[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.414      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.295 ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.415      ;
; 0.296 ; ram_bena_reg[0]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.415      ;
; 0.297 ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_rd_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.417      ;
; 0.298 ; ram_bena_reg[1]                                                                                                 ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.417      ;
; 0.300 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.420      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.420      ;
; 0.301 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.421      ;
; 0.327 ; sdram_ctrl:sdram_controller|r_rd_act                                                                            ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.447      ;
; 0.328 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.447      ;
; 0.334 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.453      ;
; 0.343 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.462      ;
; 0.350 ; seq_reg[3]                                                                                                      ; seq_reg[4]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.469      ;
; 0.350 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_rd_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.469      ;
; 0.351 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.470      ;
; 0.355 ; seq_reg[6]                                                                                                      ; seq_reg[7]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.474      ;
; 0.355 ; sdram_ctrl:sdram_controller|r_refr_act                                                                          ; sdram_ctrl:sdram_controller|r_wr_reg                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.474      ;
; 0.355 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.474      ;
; 0.356 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_psel_dly[0]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.476      ;
; 0.356 ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                                       ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.475      ;
; 0.363 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30] ; ram_di_reg[14]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.558      ;
; 0.364 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21] ; ram_di_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.559      ;
; 0.364 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25] ; ram_di_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.559      ;
; 0.365 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19] ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.560      ;
; 0.365 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27] ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.560      ;
; 0.366 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22] ; ram_di_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.561      ;
; 0.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17] ; ram_di_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.562      ;
; 0.367 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23] ; ram_di_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.562      ;
; 0.373 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24] ; ram_di_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 0.567      ;
; 0.375 ; seq_reg[11]                                                                                                     ; sdram_ctrl:sdram_controller|r_init_tmr[10]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.494      ;
; 0.375 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16] ; ram_di_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 0.569      ;
; 0.376 ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                                                                        ; sdram_ctrl:sdram_controller|r_wr_act                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.495      ;
; 0.376 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg          ; sdram_ctrl:sdram_controller|r_refr_req                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 0.566      ;
; 0.386 ; sdram_ctrl:sdram_controller|r_psel[0]                                                                           ; sdram_ctrl:sdram_controller|r_bst_stp[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.506      ;
; 0.405 ; seq_reg[10]                                                                                                     ; seq_reg[11]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.034      ; 0.523      ;
; 0.405 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]  ; ram_di_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 0.599      ;
; 0.415 ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1                                                           ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.535      ;
; 0.415 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11] ; ram_di_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 0.610      ;
; 0.416 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.605      ;
; 0.422 ; sdram_ctrl:sdram_controller|r_wr_act                                                                            ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.541      ;
; 0.433 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]  ; ram_di_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 0.627      ;
; 0.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.628      ;
; 0.439 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18] ; ram_di_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 0.633      ;
; 0.441 ; sdram_ctrl:sdram_controller|r_init_tmr[8]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.561      ;
; 0.442 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.562      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[2]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.443 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.563      ;
; 0.452 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.572      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.453 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.573      ;
; 0.454 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.574      ;
; 0.455 ; sdram_ctrl:sdram_controller|r_init_tmr[1]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.575      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[7]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[5]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.456 ; sdram_ctrl:sdram_controller|r_init_tmr[3]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.576      ;
; 0.457 ; sdram_ctrl:sdram_controller|r_init_tmr[0]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.577      ;
; 0.461 ; seq_reg[2]                                                                                                      ; seq_reg[3]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.580      ;
; 0.462 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|sdram_rdy                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.581      ;
; 0.463 ; seq_reg[8]                                                                                                      ; seq_reg[9]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.582      ;
; 0.463 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26] ; ram_di_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.090      ; 0.657      ;
; 0.465 ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                                      ; sdram_ctrl:sdram_controller|r_init_fsm[2]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.584      ;
; 0.477 ; seq_reg[1]                                                                                                      ; seq_reg[2]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.596      ;
; 0.481 ; seq_reg[4]                                                                                                      ; seq_reg[5]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.035      ; 0.600      ;
; 0.489 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.678      ;
; 0.494 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[12]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.683      ;
; 0.495 ; sdram_ctrl:sdram_controller|r_refr_req                                                                          ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.615      ;
; 0.495 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.684      ;
; 0.496 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.685      ;
; 0.497 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.686      ;
; 0.498 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg     ; ram_do_reg[13]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 0.687      ;
; 0.505 ; sdram_ctrl:sdram_controller|r_init_tmr[6]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.625      ;
; 0.506 ; sdram_ctrl:sdram_controller|r_init_tmr[4]                                                                       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.036      ; 0.626      ;
+-------+-----------------------------------------------------------------------------------------------------------------+----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Hold: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                                                                                                                                                                                                ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                                                                                                                                                  ; To Node                                                                                                                                                    ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[6]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[4]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[0]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|nmi_pending_reg                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nmiReg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pf_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[2]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|pmg_dma_state_reg[0]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p0pl_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|count_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[6]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile0|shift_reg[7]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m0pl_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[1]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[2]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[3]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[4]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[5]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player1|shift_reg[6]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|count_reg[1]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[3]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[4]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:missile3|shift_reg[5]                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m3pf_reg[2]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pf_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|p2pf_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[0]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|last_line_of_instruction_reg                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dli_nmi_reg                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|nmist_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[3]                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|m2pl_reg[3]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wsync_reg                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[2]                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[3]                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dmactl_raw_reg[5]                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[1]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|active_bk_modify_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                          ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot_reset_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[4]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[0]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[2]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|audf0_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_countdown_timer:timer0|delay_line:underflow0_delay|shift_reg[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[1]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|delay_line:serout_clock_delay|shift_reg[0]                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_clock_reg                                                      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_clock_reg                                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[66]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[90]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[70]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[42]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[75]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[65]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[78]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[34]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                             ; ps2_to_atari800:keyboard_map1|ps2_keys_reg[82]                                                                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|shift_pressed_reg      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[6]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[6]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg    ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|control_pressed_reg    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg      ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_keyboard_scanner:pokey_keyboard_scanner1|break_pressed_reg      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[7]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[7]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_active_reg                                                                                     ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_active_reg                                                                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                             ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|count_reg[1]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player2|shift_reg[0]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|gtia_player:player3|shift_reg[0]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                          ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|irqst_reg[5]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                            ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|vblank_reg                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_refresh_count|value_reg[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                            ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                   ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_store_sp2                                                                                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                           ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                                       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
; 0.187 ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.036      ; 0.307      ;
+-------+------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                                                        ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                                                                                     ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 8.892 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.085     ; 2.650      ;
; 8.892 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.085     ; 2.650      ;
; 8.908 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.633      ;
; 8.908 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.086     ; 2.633      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 2.453      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 2.453      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 2.458      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.457      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[5]                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 2.447      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.097     ; 2.453      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[0]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.098     ; 2.452      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[19]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.457      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[31]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[22]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.093     ; 2.457      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 2.458      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[29]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.456      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[29]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.456      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[29]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 2.458      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[26]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[22]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.456      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[22]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.456      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[24]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 2.445      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[24]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 2.445      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[17]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.456      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_speed_reg[7]                                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[2]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[3]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.102     ; 2.448      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[6]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 2.449      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[7]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 2.449      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[8]                                                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.102     ; 2.448      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[8]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.102     ; 2.448      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[9]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.102     ; 2.448      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[10]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[11]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[11]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[10]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|ss_n[0]                                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.113     ; 2.437      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 2.458      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.092     ; 2.458      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[30]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[14]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 2.449      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[15]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 2.449      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[14]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 2.449      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addr_reg[15]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 2.449      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.102     ; 2.448      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[0]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[1]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[4]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[5]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[3]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[2]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.096     ; 2.454      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[7]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_addrend_reg[6]                                              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.101     ; 2.449      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.104     ; 2.446      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[16]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.456      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[16]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.094     ; 2.456      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[16]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.105     ; 2.445      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[21]                                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_clock_last_reg                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_full_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.095     ; 2.455      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[0]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[3]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[4]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[5]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[6]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[7]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[9]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[8]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[7]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[6]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[5]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[4]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[2]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[3]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_holding_reg[1]                                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[2]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serout_shift_reg[1]                                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_out_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[3]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 2.447      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[0]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.110     ; 2.440      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[1]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.110     ; 2.440      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|skctl_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.099     ; 2.451      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[2]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.110     ; 2.440      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[3]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.110     ; 2.440      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|count_reg[4]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.110     ; 2.440      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|syncreset_enable_divider:enable_64_div|enabled_out_reg ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.110     ; 2.440      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[0]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|audctl_reg[6]                                          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.100     ; 2.450      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[2]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 2.447      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[1]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 2.447      ;
; 9.077 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|delay_line:stimer_delay|shift_reg[0]                   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 11.640       ; -0.103     ; 2.447      ;
+-------+---------------------------------------+-------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Recovery: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                   ;
+-------+------------------------+-------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[0]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 1.699      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[1]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 1.699      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[2]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 1.699      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[10]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 1.699      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[11]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 1.699      ;
; 9.755 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[12]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 1.699      ;
; 9.756 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[5]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.138     ; 1.686      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[2]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 1.641      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[1]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 1.641      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[12]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 1.641      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[10]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 1.641      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[0]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 1.641      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[11]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 1.641      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[3]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.135     ; 1.688      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[4]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.140     ; 1.683      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[7]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.134     ; 1.689      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[8]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.126     ; 1.697      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[13]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.130     ; 1.693      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[14]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.130     ; 1.693      ;
; 9.757 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[15]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.130     ; 1.693      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[5]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.192     ; 1.628      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[6]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.134     ; 1.688      ;
; 9.758 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_o[9]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.132     ; 1.690      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[3]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.189     ; 1.630      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[15]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 1.635      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[13]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 1.635      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[8]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.180     ; 1.639      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[14]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.184     ; 1.635      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[4]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.194     ; 1.625      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[7]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 1.631      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.773      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.773      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.773      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.773      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.773      ;
; 9.759 ; sdram_reset_ctrl_n_reg ; ram_di_reg[12]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.773      ;
; 9.760 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[6]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.188     ; 1.630      ;
; 9.760 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rddata[9]               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.186     ; 1.632      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[0]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.703      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[1]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.703      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[2]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.703      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[3]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.703      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[6]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.709      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[7]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.104     ; 1.709      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.703      ;
; 9.767 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]          ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.110     ; 1.703      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[4]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.101     ; 1.711      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[5]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.103     ; 1.709      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[8]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.710      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ba[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 1.704      ;
; 9.768 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.102     ; 1.710      ;
; 9.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.737      ;
; 9.803 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.737      ;
; 9.885 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 1.587      ;
; 9.885 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 1.587      ;
; 9.885 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 1.587      ;
; 9.885 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.108     ; 1.587      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.544      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.544      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.544      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.539      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.539      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.544      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.544      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.539      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.539      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.095     ; 1.539      ;
; 9.993 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.544      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.087     ; 1.546      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.545      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.545      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.545      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.545      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.545      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.088     ; 1.545      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.089     ; 1.544      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.089     ; 1.544      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.089     ; 1.544      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.994 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.085     ; 1.548      ;
; 9.995 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.542      ;
; 9.995 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                        ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 11.640       ; -0.090     ; 1.542      ;
+-------+------------------------+-------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                                                                        ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node              ; To Node                                                   ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 1.212 ; sdram_reset_ctrl_n_reg ; seq_reg[0]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.405      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_req                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[19]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[31]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[18]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[17]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[22]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[28]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[29]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[26]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[24]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[30]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[16]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[21]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[27]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[20]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[12]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[25]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.409      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_request_reg                                         ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel[0]                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_request_complete_reg                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_do_reg[23]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[1]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[3]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[5]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[6]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.402      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[7]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.402      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[9]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[11]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[13]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.402      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[14]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.402      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; ram_di_reg[15]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.086      ; 1.402      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dq_oe                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.407      ;
; 1.212 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.096      ; 1.412      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[1]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[2]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[3]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[4]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[5]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[6]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[7]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[8]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[9]                                                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[10]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.410      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; seq_reg[11]                                               ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.092      ; 1.409      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.092      ; 1.409      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.092      ; 1.409      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.092      ; 1.409      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.092      ; 1.409      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|sdram_rdy                     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.092      ; 1.409      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_refr_act                    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.408      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.408      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_act                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.406      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.406      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_rd_reg                      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.091      ; 1.408      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[0]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.406      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.406      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; ram_bena_reg[1]                                           ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.406      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.089      ; 1.406      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.396      ;
; 1.213 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.079      ; 1.396      ;
; 1.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_ras_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.456      ;
; 1.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cas_n                 ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.456      ;
; 1.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_we_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.456      ;
; 1.302 ; sdram_reset_ctrl_n_reg ; sdram_ctrl:sdram_controller|r_sdram_cs_n                  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.076      ; 1.456      ;
; 1.384 ; sdram_reset_ctrl_n_reg ; ram_do_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.581      ;
; 1.384 ; sdram_reset_ctrl_n_reg ; ram_do_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.093      ; 1.581      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; ram_di_reg[0]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.600      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; ram_di_reg[2]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.600      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; ram_di_reg[4]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.600      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; ram_di_reg[8]                                             ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.600      ;
; 1.411 ; sdram_reset_ctrl_n_reg ; ram_di_reg[10]                                            ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000        ; 0.085      ; 1.600      ;
+-------+------------------------+-----------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Removal: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                   ;
+-------+---------------------------------------+-------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; Slack ; From Node                             ; To Node                                               ; Launch Clock                                                                   ; Latch Clock                                                                    ; Relationship ; Clock Skew ; Data Delay ;
+-------+---------------------------------------+-------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+
; 2.128 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.098      ; 2.330      ;
; 2.128 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.326      ;
; 2.128 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.094      ; 2.326      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.091      ; 2.329      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[9]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.134 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[11]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.324      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 2.329      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 2.329      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 2.329      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[30]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]     ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.096      ; 2.335      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[17]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 2.321      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[28]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 2.321      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[28]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[29]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.334      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[26]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[22]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[24]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[24]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 2.321      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[17]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[18]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.090      ; 2.329      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[31]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[19]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[21]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[21]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.334      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[27]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[20]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[20]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 2.321      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[6]   ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.085      ; 2.324      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[1]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 2.321      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[13]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[4]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.082      ; 2.321      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[12]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[25]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.095      ; 2.334      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[25]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[0]       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.323      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[10]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[14]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[15]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[23]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[0]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[1]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[2]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[3]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[4]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[5]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[6]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[7]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[8]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[9]  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[10] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[11] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[12] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[13] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[14] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.135 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[15] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.086      ; 2.325      ;
; 2.136 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.332      ;
; 2.136 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]    ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.084      ; 2.324      ;
; 2.136 ; sdram_ctrl:sdram_controller|sdram_rdy ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]      ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000        ; 0.092      ; 2.332      ;
+-------+---------------------------------------+-------------------------------------------------------+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+--------------+------------+------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]'                                                                                         ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; Slack ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                    ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[0]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[10]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[11]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[12]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[13]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[14]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[15]                                            ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[1]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[2]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[3]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[4]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[5]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[6]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[7]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[8]                                             ;
; 5.605 ; 5.821        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[9]                                             ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[0]                                           ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_bena_reg[1]                                           ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[16]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[17]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[18]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[19]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[20]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[21]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[22]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[23]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[24]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[25]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[26]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[27]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[28]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[29]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[30]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_do_reg[31]                                            ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[0]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[1]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[2]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[3]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[4]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[5]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[6]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[7]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[8]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[9]                 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[10]~_Duplicate_1 ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_addr[9]~_Duplicate_1  ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[0]              ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_dqm_n[1]              ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_act                      ;
; 5.606 ; 5.822        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_bctr[0]                  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|ap1_rd_bst_act                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_bst_stp[0]                  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[0]                 ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[1]                 ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_fsm[2]                 ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_init_tmr[10]                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel[0]                     ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_psel_dly[0]                 ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_act                      ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_bctr[0]                  ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rd_reg                      ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[0]                   ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[10]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[11]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[12]                  ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[1]                   ;
; 5.607 ; 5.762        ; 0.155          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_rddata[2]                   ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_act                    ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_refr_req                    ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_sdram_cs_n~_Duplicate_1     ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|r_wr_reg                      ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_ctrl:sdram_controller|sdram_rdy                     ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_complete_reg                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; sdram_request_reg                                         ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[0]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[10]                                               ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[11]                                               ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[1]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[2]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[3]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[4]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[5]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[6]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[7]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[8]                                                ;
; 5.607 ; 5.823        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; seq_reg[9]                                                ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[0]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[10]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[11]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[12]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[13]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[14]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[15]                                            ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[1]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[2]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[3]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[4]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[5]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[6]                                             ;
; 5.608 ; 5.824        ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; ram_di_reg[7]                                             ;
+-------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+-----------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]'                                                                                                                                                                                                                       ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                          ; Clock Edge ; Target                                                                                                                                                                                 ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_l|altsyncram:Ram0_rtl_0|altsyncram_cp71:auto_generated|ram_block1a2~porta_address_reg0 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey_mixer:pokey_mixer_r|altsyncram:Ram0_rtl_0|altsyncram_cp71:auto_generated|ram_block1a2~porta_address_reg0 ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a0~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a10~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a14~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a20~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a21~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a23~porta_address_reg0                                                                                  ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a2~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a3~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a6~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a7~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a8~porta_address_reg0                                                                                   ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                      ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                            ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                        ;
; 17.206 ; 17.436       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                              ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a11~porta_address_reg0                                                                                  ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a17~porta_address_reg0                                                                                  ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a1~porta_address_reg0                                                                                   ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a4~porta_address_reg0                                                                                   ;
; 17.207 ; 17.437       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpu_rom:zpu_rom1|altsyncram:ROM_rtl_0|altsyncram_cc71:auto_generated|ram_block1a5~porta_address_reg0                                                                                   ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                       ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                             ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_31_24|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                       ;
; 17.208 ; 17.438       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_7_0|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                         ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_address_reg0                                                       ;
; 17.209 ; 17.439       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_we_reg                                                             ;
; 17.210 ; 17.440       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram_15_8|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                        ;
; 17.211 ; 17.441       ; 0.230          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|generic_ram_infer:ram23_16|altsyncram:ram_block_rtl_0|altsyncram_9f41:auto_generated|ram_block1a0~porta_datain_reg0                                                        ;
; 17.240 ; 17.424       ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                                                                    ;
; 17.240 ; 17.424       ; 0.184          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                                                                   ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[28][5]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[29][5]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[30][5]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[30][6]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[31][5]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[31][6]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[0][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[10][2]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[11][2]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[12][2]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[13][2]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[14][2]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[15][2]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[1][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[2][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[3][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[4][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[5][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[6][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[7][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[8][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:vscrol_delay|shift_reg[9][2]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[1]                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[2]                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[3]                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|A[7]                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[1]                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|X[2]                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irq_n_reg                                                                                         ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[0]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[1]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[2]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[4]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqen_reg[5]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[0]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[1]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[2]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[4]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|irqst_reg[5]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|keyboard_overrun_reg                                                                              ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[10]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[11]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[12]                                                     ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pokey_poly_17_9:poly_17_19_lfsr|shift_reg[9]                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[4]                                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|pot0_reg[5]                                                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_ip_framing_reg                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_ip_overrun_reg                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_reg[4]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serin_reg[5]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[1]                                                                            ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[2]                                                                            ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serout_bitcount_reg[3]                                                                            ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|sio_in_reg                                                                                        ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[0]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|skctl_reg[1]                                                                                      ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|synchronizer:sio_in1_synchronizer|ff_reg[0]                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|synchronizer:sio_in1_synchronizer|ff_reg[1]                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|synchronizer:sio_in1_synchronizer|ff_reg[2]                                                       ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serial_ip_framing_reg                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|serial_ip_overrun_reg                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[0]                                                                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[1]                                                                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[2]                                                                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; enable_divider:enable_179_clock_div_zpu_pokey|count_reg[3]                                                                                                                             ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                                                                                                          ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|enable_divider:enable_div|count_reg[2]                                                                                            ;
; 17.245 ; 17.461       ; 0.216          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; Rise       ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|enable_divider:enable_div|count_reg[3]                                                                                            ;
+--------+--------------+----------------+------------------+--------------------------------------------------------------------------------+------------+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: '\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]'                                                                                                                                    ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; Slack  ; Actual Width ; Required Width ; Type             ; Clock                                                                         ; Clock Edge ; Target                                                                                              ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.437 ; 17.437       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
; 17.451 ; 17.451       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.458 ; 17.458       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|inclk[0] ;
; 17.462 ; 17.462       ; 0.000          ; Low Pulse Width  ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|wire_pll1_clk[0]~clkctrl|outclk   ;
; 17.468 ; 17.468       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]                    ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]                      ;
; 17.483 ; 17.483       ; 0.000          ; High Pulse Width ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|observablevcoout            ;
+--------+--------------+----------------+------------------+-------------------------------------------------------------------------------+------------+-----------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast 1200mV 0C Model Minimum Pulse Width: 'FPGA_CLK'                                                                                                                         ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; Slack   ; Actual Width ; Required Width ; Type             ; Clock    ; Clock Edge ; Target                                                                                  ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 99.405  ; 99.405       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 99.439  ; 99.439       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 99.450  ; 99.450       ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.000 ; 100.000      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.000 ; 100.000      ; 0.000          ; Low Pulse Width  ; FPGA_CLK ; Rise       ; FPGA_CLK~input|i                                                                        ;
; 100.549 ; 100.549      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]         ;
; 100.561 ; 100.561      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; FPGA_CLK~input|o                                                                        ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]           ;
; 100.592 ; 100.592      ; 0.000          ; High Pulse Width ; FPGA_CLK ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|observablevcoout ;
; 196.000 ; 200.000      ; 4.000          ; Port Rate        ; FPGA_CLK ; Rise       ; FPGA_CLK                                                                                ;
+---------+--------------+----------------+------------------+----------+------------+-----------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.467 ; 2.025 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.467 ; 2.025 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.467 ; 2.025 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.486 ; 2.044 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.491 ; 2.049 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.489 ; 2.047 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.485 ; 2.043 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.495 ; 2.053 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.493 ; 2.051 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.487 ; 2.045 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.477 ; 2.035 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.471 ; 2.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.481 ; 2.039 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 3.146 ; 3.538 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 2.004 ; 2.500 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 2.188 ; 2.669 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 2.219 ; 2.699 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 2.259 ; 2.725 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 3.146 ; 3.538 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 3.027 ; 3.439 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 1.954 ; 2.470 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 2.218 ; 2.699 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 2.353 ; 2.800 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 2.278 ; 2.748 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 3.027 ; 3.439 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 3.505 ; 4.330 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 3.060 ; 3.807 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 1.977 ; 2.458 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.011 ; -1.569 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.488 ; -1.968 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.488 ; -1.968 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.679 ; -2.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.708 ; -2.184 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.734 ; -2.181 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.680 ; -2.148 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.418 ; -1.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.418 ; -1.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.707 ; -2.184 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.837 ; -2.281 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.765 ; -2.231 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.505 ; -2.008 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.945 ; -3.760 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.512 ; -3.246 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.476 ; -1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                      ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.597 ; 1.446 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.596 ; 1.445 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.604 ; 1.453 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.613 ; 1.462 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.588 ; 2.294 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.615 ; 1.464 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.625 ; 1.474 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.607 ; 1.456 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.609 ; 1.458 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.582 ; 2.288 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.594 ; 2.300 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.760 ; 1.614 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.760 ; 1.614 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.760 ; 1.614 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.627 ; 2.349 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.622 ; 2.344 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 1.163 ; 1.075 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.685 ; 1.535 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.695 ; 1.545 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.640 ; 2.362 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.780 ; 1.634 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.770 ; 1.624 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.632 ; 2.354 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.756 ; 1.610 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.766 ; 1.620 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 2.480 ; 2.331 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.480 ; 2.331 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.746 ; 1.721 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.619 ; 1.468 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.629 ; 1.478 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.426 ; 3.986 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.825 ; 1.958 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 2.183 ; 2.334 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.753 ; 4.360 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.824 ; 1.720 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 5.452 ; 6.038 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 3.908 ; 3.959 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 5.413 ; 5.975 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 4.126 ; 4.274 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 5.452 ; 6.038 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 5.263 ; 5.733 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 5.263 ; 5.733 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 3.698 ; 3.718 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 3.617 ; 3.737 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 3.065 ; 3.176 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 3.969 ; 3.488 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 3.873 ; 3.890 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 3.867 ; 3.890 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 3.873 ; 3.885 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 3.426 ; 3.454 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 3.644 ; 3.669 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 1.088 ; 1.054 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 8.215 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 8.162 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.351 ; 1.207 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.324 ; 1.303 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.028 ; 1.888 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.324 ; 1.303 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.014 ; 3.571 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.412 ; 1.541 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.747 ; 1.891 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.325 ; 3.925 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.401 ; 1.302 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.834 ; 1.983 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.927 ; 1.985 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 3.464 ; 3.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.834 ; 1.983 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 3.830 ; 4.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.590 ; 1.684 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 3.411 ; 3.888 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.765 ; 1.793 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.802 ; 1.823 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.590 ; 1.684 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 3.425 ; 2.948 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.558 ; 1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.829 ; 1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.558 ; 1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.592 ; 1.627 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.689 ; 1.710 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.842 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.788 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Output Enable Times                                                                                                                      ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.296 ; 2.269 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.296 ; 2.269 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.296 ; 2.269 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.296 ; 2.269 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.469 ; 2.442 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.659 ; 2.632 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.670 ; 2.643 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.843 ; 2.816 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.853 ; 2.826 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.007 ; 2.980 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.838 ; 2.811 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.658 ; 2.631 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.658 ; 2.631 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.648 ; 2.621 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.640 ; 2.613 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.630 ; 2.603 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.640 ; 2.613 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 3.137 ; 2.761 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Enable Times                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 0.989 ; 0.989 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 0.989 ; 0.989 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 0.989 ; 0.989 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 0.989 ; 0.989 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.155 ; 1.155 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.339 ; 1.339 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.349 ; 1.349 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.514 ; 1.514 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.525 ; 1.525 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.673 ; 1.673 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.511 ; 1.511 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.338 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.338 ; 1.338 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.328 ; 1.328 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.320 ; 1.320 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.310 ; 1.310 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.320 ; 1.320 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.610 ; 2.249 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Disable Times                                                                                                                             ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 2.376     ; 2.376     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 2.376     ; 2.376     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 2.376     ; 2.376     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 2.376     ; 2.376     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 2.564     ; 2.564     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 2.773     ; 2.773     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 2.789     ; 2.789     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 2.980     ; 2.980     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 2.980     ; 2.980     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.165     ; 3.165     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 2.980     ; 2.980     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 2.784     ; 2.784     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 2.784     ; 2.784     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 2.774     ; 2.774     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 2.767     ; 2.767     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 2.757     ; 2.757     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 2.767     ; 2.767     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.924     ; 3.300     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Output Disable Times                                                                                                                     ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; 0 to Hi-Z ; 1 to Hi-Z ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 1.067     ; 1.184     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 1.067     ; 1.184     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 1.067     ; 1.184     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 1.067     ; 1.184     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 1.247     ; 1.364     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 1.447     ; 1.564     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 1.463     ; 1.580     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 1.646     ; 1.763     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 1.647     ; 1.764     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 1.824     ; 1.941     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 1.647     ; 1.764     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 1.458     ; 1.575     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 1.458     ; 1.575     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 1.448     ; 1.565     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 1.442     ; 1.559     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 1.432     ; 1.549     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 1.442     ; 1.559     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SD_CMD        ; FPGA_CLK   ; 2.405     ; 2.766     ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-----------+-----------+------------+--------------------------------------------------------------------------------+


---------------------------------------------
; Fast 1200mV 0C Model Metastability Report ;
---------------------------------------------
No synchronizer chains to report.


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Multicorner Timing Analysis Summary                                                                                                        ;
+---------------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+
; Clock                                                                           ; Setup ; Hold  ; Recovery ; Removal ; Minimum Pulse Width ;
+---------------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+
; Worst-case Slack                                                                ; 0.853 ; 0.187 ; 5.551    ; 1.212   ; 5.517               ;
;  FPGA_CLK                                                                       ; N/A   ; N/A   ; N/A      ; N/A     ; 99.405              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.853 ; 0.187 ; 7.532    ; 1.212   ; 5.517               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2.790 ; 0.187 ; 5.551    ; 2.128   ; 17.114              ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A   ; N/A   ; N/A      ; N/A     ; 17.423              ;
; Design-wide TNS                                                                 ; 0.0   ; 0.0   ; 0.0      ; 0.0     ; 0.0                 ;
;  FPGA_CLK                                                                       ; N/A   ; N/A   ; N/A      ; N/A     ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 0.000 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 0.000 ; 0.000 ; 0.000    ; 0.000   ; 0.000               ;
;  \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]  ; N/A   ; N/A   ; N/A      ; N/A     ; 0.000               ;
+---------------------------------------------------------------------------------+-------+-------+----------+---------+---------------------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Times                                                                                                                              ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; 3.012 ; 3.119 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; 3.040 ; 3.147 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; 3.038 ; 3.145 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; 3.034 ; 3.141 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; 3.046 ; 3.153 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; 3.032 ; 3.139 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; 3.036 ; 3.143 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; 3.014 ; 3.121 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; 3.024 ; 3.131 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; 6.382 ; 6.899 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; 4.055 ; 4.268 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; 4.415 ; 4.619 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; 4.455 ; 4.694 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; 4.594 ; 4.844 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; 6.382 ; 6.899 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; 6.192 ; 6.643 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; 3.964 ; 4.177 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; 4.446 ; 4.681 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; 4.783 ; 5.002 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; 4.651 ; 4.862 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; 6.192 ; 6.643 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; 7.323 ; 7.640 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; 6.343 ; 6.575 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; 3.946 ; 4.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Times                                                                                                                                 ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port     ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_DQ[*]   ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]  ; FPGA_CLK   ; -1.001 ; -1.559 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]  ; FPGA_CLK   ; -1.020 ; -1.578 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]  ; FPGA_CLK   ; -1.025 ; -1.583 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]  ; FPGA_CLK   ; -1.023 ; -1.581 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]  ; FPGA_CLK   ; -1.019 ; -1.577 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]  ; FPGA_CLK   ; -1.029 ; -1.587 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]  ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]  ; FPGA_CLK   ; -1.027 ; -1.585 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11] ; FPGA_CLK   ; -1.021 ; -1.579 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12] ; FPGA_CLK   ; -1.011 ; -1.569 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14] ; FPGA_CLK   ; -1.005 ; -1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15] ; FPGA_CLK   ; -1.015 ; -1.573 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; JOY1_n[*]     ; FPGA_CLK   ; -1.488 ; -1.968 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[0]    ; FPGA_CLK   ; -1.488 ; -1.968 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[1]    ; FPGA_CLK   ; -1.679 ; -2.156 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[2]    ; FPGA_CLK   ; -1.708 ; -2.184 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[3]    ; FPGA_CLK   ; -1.734 ; -2.181 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY1_n[4]    ; FPGA_CLK   ; -1.680 ; -2.148 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; JOY2_n[*]     ; FPGA_CLK   ; -1.418 ; -1.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[0]    ; FPGA_CLK   ; -1.418 ; -1.921 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[1]    ; FPGA_CLK   ; -1.707 ; -2.184 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[2]    ; FPGA_CLK   ; -1.837 ; -2.281 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[3]    ; FPGA_CLK   ; -1.765 ; -2.231 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  JOY2_n[4]    ; FPGA_CLK   ; -1.505 ; -2.008 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_CLK      ; FPGA_CLK   ; -2.945 ; -3.760 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; PS2K_DAT      ; FPGA_CLK   ; -2.512 ; -3.246 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT0       ; FPGA_CLK   ; -1.476 ; -1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
+---------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------+
; Clock to Output Times                                                                                                                        ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise   ; Fall   ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 3.313  ; 3.077  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 3.317  ; 3.081  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 3.326  ; 3.090  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 3.336  ; 3.100  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 3.346  ; 3.110  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 3.323  ; 3.087  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 3.325  ; 3.089  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 4.578  ; 4.128  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 4.590  ; 4.140  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 3.617  ; 3.360  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 3.617  ; 3.360  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 3.617  ; 3.360  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 4.637  ; 4.189  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 4.633  ; 4.185  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 2.563  ; 2.365  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 3.507  ; 3.264  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 3.519  ; 3.276  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 3.639  ; 3.382  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 4.657  ; 4.209  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 3.644  ; 3.387  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 3.644  ; 3.387  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 3.634  ; 3.377  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 4.648  ; 4.200  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 3.614  ; 3.357  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 3.624  ; 3.367  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 4.900  ; 5.257  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 4.900  ; 5.257  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 3.576  ; 3.952  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 3.335  ; 3.099  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 3.345  ; 3.109  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 6.559  ; 6.787  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 4.139  ; 3.924  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 5.164  ; 4.685  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 7.313  ; 7.410  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 3.726  ; 3.933  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 11.350 ; 11.342 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 8.773  ; 8.650  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 10.997 ; 11.171 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 9.349  ; 9.152  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 11.350 ; 11.342 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 10.605 ; 10.837 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 10.605 ; 10.837 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 8.516  ; 8.221  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 8.285  ; 8.078  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 7.219  ; 6.853  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 6.861  ; 6.650  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 8.743  ; 8.440  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 8.743  ; 8.437  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 8.687  ; 8.440  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 7.763  ; 7.530  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 8.365  ; 8.082  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 2.486  ; 2.369  ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 9.222  ;        ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;        ; 8.951  ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+--------+--------+------------+--------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------+
; Minimum Clock to Output Times                                                                                                              ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; Data Port       ; Clock Port ; Rise  ; Fall  ; Clock Edge ; Clock Reference                                                                ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+
; SDRAM_A[*]      ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[0]     ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[1]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[2]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[3]     ; FPGA_CLK   ; 1.179 ; 1.030 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[4]     ; FPGA_CLK   ; 1.178 ; 1.029 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[5]     ; FPGA_CLK   ; 1.186 ; 1.037 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[6]     ; FPGA_CLK   ; 1.195 ; 1.046 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[7]     ; FPGA_CLK   ; 2.192 ; 1.898 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[8]     ; FPGA_CLK   ; 1.197 ; 1.048 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[9]     ; FPGA_CLK   ; 1.207 ; 1.058 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_A[10]    ; FPGA_CLK   ; 1.189 ; 1.040 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_BA[*]     ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[0]    ; FPGA_CLK   ; 1.191 ; 1.042 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_BA[1]    ; FPGA_CLK   ; 2.186 ; 1.892 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CAS_N     ; FPGA_CLK   ; 2.198 ; 1.904 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_CS_N      ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQ[*]     ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[0]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[1]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[2]    ; FPGA_CLK   ; 1.341 ; 1.197 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[3]    ; FPGA_CLK   ; 2.232 ; 1.954 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[4]    ; FPGA_CLK   ; 2.227 ; 1.949 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[5]    ; FPGA_CLK   ; 0.768 ; 0.680 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[6]    ; FPGA_CLK   ; 1.266 ; 1.118 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[7]    ; FPGA_CLK   ; 1.276 ; 1.128 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[8]    ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[9]    ; FPGA_CLK   ; 2.245 ; 1.967 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[10]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[11]   ; FPGA_CLK   ; 1.361 ; 1.217 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[12]   ; FPGA_CLK   ; 1.351 ; 1.207 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[13]   ; FPGA_CLK   ; 2.237 ; 1.959 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[14]   ; FPGA_CLK   ; 1.337 ; 1.193 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQ[15]   ; FPGA_CLK   ; 1.347 ; 1.203 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_DQM_n[*]  ; FPGA_CLK   ; 1.324 ; 1.303 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[0] ; FPGA_CLK   ; 2.028 ; 1.888 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
;  SDRAM_DQM_n[1] ; FPGA_CLK   ; 1.324 ; 1.303 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_RAS_N     ; FPGA_CLK   ; 1.201 ; 1.052 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; SDRAM_WE_N      ; FPGA_CLK   ; 1.211 ; 1.062 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ;
; AUDIO_L         ; FPGA_CLK   ; 3.014 ; 3.571 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; AUDIO_R         ; FPGA_CLK   ; 1.412 ; 1.541 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CLK          ; FPGA_CLK   ; 1.747 ; 1.891 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_CMD          ; FPGA_CLK   ; 3.325 ; 3.925 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SD_DAT3         ; FPGA_CLK   ; 1.401 ; 1.302 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_B[*]        ; FPGA_CLK   ; 1.834 ; 1.983 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[0]       ; FPGA_CLK   ; 1.927 ; 1.985 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[1]       ; FPGA_CLK   ; 3.464 ; 3.991 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[2]       ; FPGA_CLK   ; 1.834 ; 1.983 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_B[3]       ; FPGA_CLK   ; 3.830 ; 4.420 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_G[*]        ; FPGA_CLK   ; 1.590 ; 1.684 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[0]       ; FPGA_CLK   ; 3.411 ; 3.888 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[1]       ; FPGA_CLK   ; 1.765 ; 1.793 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[2]       ; FPGA_CLK   ; 1.802 ; 1.823 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_G[3]       ; FPGA_CLK   ; 1.590 ; 1.684 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_HS          ; FPGA_CLK   ; 3.425 ; 2.948 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_R[*]        ; FPGA_CLK   ; 1.558 ; 1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[0]       ; FPGA_CLK   ; 1.829 ; 1.857 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[1]       ; FPGA_CLK   ; 1.558 ; 1.563 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[2]       ; FPGA_CLK   ; 1.592 ; 1.627 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
;  VGA_R[3]       ; FPGA_CLK   ; 1.689 ; 1.710 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; VGA_VS          ; FPGA_CLK   ; 0.692 ; 0.658 ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ;
; SDRAM_CLK       ; FPGA_CLK   ; 7.842 ;       ; Rise       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
; SDRAM_CLK       ; FPGA_CLK   ;       ; 7.788 ; Fall       ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2] ;
+-----------------+------------+-------+-------+------------+--------------------------------------------------------------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Board Trace Model Assignments                                                                                                                                                                                                                                                                                                                                                                                     ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; Pin            ; I/O Standard ; Near Tline Length ; Near Tline L per Length ; Near Tline C per Length ; Near Series R ; Near Differential R ; Near Pull-up R ; Near Pull-down R ; Near C ; Far Tline Length ; Far Tline L per Length ; Far Tline C per Length ; Far Series R ; Far Pull-up R ; Far Pull-down R ; Far C ; Termination Voltage ; Far Differential R ; EBD File Name ; EBD Signal Name ; EBD Far-end ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 in              ; 0 H/in                  ; 0 F/in                  ; short         ; -                   ; open           ; open             ; open   ; 0 in             ; 0 H/in                 ; 0 F/in                 ; short        ; open          ; open            ; open  ; 0 V                 ; -                  ; n/a           ; n/a             ; n/a         ;
+----------------+--------------+-------------------+-------------------------+-------------------------+---------------+---------------------+----------------+------------------+--------+------------------+------------------------+------------------------+--------------+---------------+-----------------+-------+---------------------+--------------------+---------------+-----------------+-------------+


+-----------------------------------------------------------------+
; Input Transition Times                                          ;
+--------------+--------------+-----------------+-----------------+
; Pin          ; I/O Standard ; 10-90 Rise Time ; 90-10 Fall Time ;
+--------------+--------------+-----------------+-----------------+
; PS2M_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2M_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[5]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[0]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[1]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[2]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[3]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[4]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[5]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[6]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[7]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[8]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[9]  ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[10] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[11] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[12] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[13] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[14] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; SDRAM_DQ[15] ; 3.3-V LVTTL  ; 2640 ps         ; 2640 ps         ;
; FPGA_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[4]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[1]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY1_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[3]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[0]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; JOY2_n[2]    ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; SD_DAT0      ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_CLK     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
; PS2K_DAT     ; 3.3-V LVCMOS ; 2640 ps         ; 2640 ps         ;
+--------------+--------------+-----------------+-----------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Slow Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.013 V            ; 0.091 V                              ; 0.178 V                              ; 1.33e-09 s                  ; 1.36e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.013 V           ; 0.091 V                             ; 0.178 V                             ; 1.33e-09 s                 ; 1.36e-09 s                 ; Yes                       ; Yes                       ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.08 V              ; -0.00108 V          ; 0.089 V                              ; 0.161 V                              ; 7.68e-09 s                  ; 7.97e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.08 V             ; -0.00108 V         ; 0.089 V                             ; 0.161 V                             ; 7.68e-09 s                 ; 7.97e-09 s                 ; Yes                       ; Yes                       ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 8.46e-07 V                   ; 3.09 V              ; -0.011 V            ; 0.146 V                              ; 0.189 V                              ; 1.76e-09 s                  ; 1.77e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 8.46e-07 V                  ; 3.09 V             ; -0.011 V           ; 0.146 V                             ; 0.189 V                             ; 1.76e-09 s                 ; 1.77e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.13 V              ; -0.0522 V           ; 0.298 V                              ; 0.208 V                              ; 6.96e-10 s                  ; 6.33e-10 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.13 V             ; -0.0522 V          ; 0.298 V                             ; 0.208 V                             ; 6.96e-10 s                 ; 6.33e-10 s                 ; Yes                       ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 7.73e-07 V                   ; 3.08 V              ; -0.00469 V          ; 0.309 V                              ; 0.24 V                               ; 5.8e-09 s                   ; 4.65e-09 s                  ; No                         ; Yes                        ; 3.08 V                      ; 7.73e-07 V                  ; 3.08 V             ; -0.00469 V         ; 0.309 V                             ; 0.24 V                              ; 5.8e-09 s                  ; 4.65e-09 s                 ; No                        ; Yes                       ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.00154 V          ; 0.08 V                               ; 0.145 V                              ; 7.32e-09 s                  ; 7.58e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.00154 V         ; 0.08 V                              ; 0.145 V                             ; 7.32e-09 s                 ; 7.58e-09 s                 ; Yes                       ; Yes                       ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.08 V                       ; 1.26e-06 V                   ; 3.09 V              ; -0.0135 V           ; 0.078 V                              ; 0.093 V                              ; 9.48e-10 s                  ; 1.01e-09 s                  ; Yes                        ; Yes                        ; 3.08 V                      ; 1.26e-06 V                  ; 3.09 V             ; -0.0135 V          ; 0.078 V                             ; 0.093 V                             ; 9.48e-10 s                 ; 1.01e-09 s                 ; Yes                       ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.12 V              ; -0.0417 V           ; 0.221 V                              ; 0.245 V                              ; 1.09e-09 s                  ; 8.59e-10 s                  ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.12 V             ; -0.0417 V          ; 0.221 V                             ; 0.245 V                             ; 1.09e-09 s                 ; 8.59e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.08 V              ; -0.00384 V          ; 0.283 V                              ; 0.244 V                              ; 6.17e-09 s                  ; 4.9e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.08 V             ; -0.00384 V         ; 0.283 V                             ; 0.244 V                             ; 6.17e-09 s                 ; 4.9e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.08 V                       ; 5.19e-07 V                   ; 3.11 V              ; -0.0313 V           ; 0.287 V                              ; 0.284 V                              ; 1.36e-09 s                  ; 1.1e-09 s                   ; No                         ; Yes                        ; 3.08 V                      ; 5.19e-07 V                  ; 3.11 V             ; -0.0313 V          ; 0.287 V                             ; 0.284 V                             ; 1.36e-09 s                 ; 1.1e-09 s                  ; No                        ; Yes                       ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fast Corner Signal Integrity Metrics                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; Pin            ; I/O Standard ; Board Delay on Rise ; Board Delay on Fall ; Steady State Voh at FPGA Pin ; Steady State Vol at FPGA Pin ; Voh Max at FPGA Pin ; Vol Min at FPGA Pin ; Ringback Voltage on Rise at FPGA Pin ; Ringback Voltage on Fall at FPGA Pin ; 10-90 Rise Time at FPGA Pin ; 90-10 Fall Time at FPGA Pin ; Monotonic Rise at FPGA Pin ; Monotonic Fall at FPGA Pin ; Steady State Voh at Far-end ; Steady State Vol at Far-end ; Voh Max at Far-end ; Vol Min at Far-end ; Ringback Voltage on Rise at Far-end ; Ringback Voltage on Fall at Far-end ; 10-90 Rise Time at Far-end ; 90-10 Fall Time at Far-end ; Monotonic Rise at Far-end ; Monotonic Fall at Far-end ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+
; VGA_VS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_HS         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_B[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; VGA_B[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_B[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.52 V              ; -0.0514 V           ; 0.253 V                              ; 0.324 V                              ; 8.77e-10 s                  ; 8.98e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.52 V             ; -0.0514 V          ; 0.253 V                             ; 0.324 V                             ; 8.77e-10 s                 ; 8.98e-10 s                 ; No                        ; No                        ;
; VGA_B[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; VGA_G[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; VGA_G[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_G[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[0]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[1]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[2]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; VGA_R[3]       ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; AUDIO_L        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.47 V              ; -0.00709 V          ; 0.326 V                              ; 0.34 V                               ; 5.02e-09 s                  ; 5.43e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.47 V             ; -0.00709 V         ; 0.326 V                             ; 0.34 V                              ; 5.02e-09 s                 ; 5.43e-09 s                 ; No                        ; No                        ;
; AUDIO_R        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 2.1e-07 V                    ; 3.51 V              ; -0.0419 V           ; 0.296 V                              ; 0.24 V                               ; 1.12e-09 s                  ; 1.29e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 2.1e-07 V                   ; 3.51 V             ; -0.0419 V          ; 0.296 V                             ; 0.24 V                              ; 1.12e-09 s                 ; 1.29e-09 s                 ; No                        ; No                        ;
; SDRAM_BA[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_BA[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_CS_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_RAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CAS_N    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_WE_N     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[0] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_DQM_n[1] ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_CLK      ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[0]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[1]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[2]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[3]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[4]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[5]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[6]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[7]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SDRAM_A[8]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[9]     ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[10]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[11]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.59 V              ; -0.0873 V           ; 0.332 V                              ; 0.189 V                              ; 4.6e-10 s                   ; 4.2e-10 s                   ; No                         ; Yes                        ; 3.46 V                      ; 1.9e-07 V                   ; 3.59 V             ; -0.0873 V          ; 0.332 V                             ; 0.189 V                             ; 4.6e-10 s                  ; 4.2e-10 s                  ; No                        ; Yes                       ;
; SDRAM_A[12]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.9e-07 V                    ; 3.48 V              ; -0.0142 V           ; 0.362 V                              ; 0.291 V                              ; 3.89e-09 s                  ; 3.25e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 1.9e-07 V                   ; 3.48 V             ; -0.0142 V          ; 0.362 V                             ; 0.291 V                             ; 3.89e-09 s                 ; 3.25e-09 s                 ; No                        ; No                        ;
; SD_CLK         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SD_CMD         ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.47 V              ; -0.0076 V           ; 0.323 V                              ; 0.334 V                              ; 4.77e-09 s                  ; 5.17e-09 s                  ; No                         ; No                         ; 3.46 V                      ; 3.1e-07 V                   ; 3.47 V             ; -0.0076 V          ; 0.323 V                             ; 0.334 V                             ; 4.77e-09 s                 ; 5.17e-09 s                 ; No                        ; No                        ;
; SD_DAT3        ; 3.3-V LVCMOS ; 0 s                 ; 0 s                 ; 3.46 V                       ; 3.1e-07 V                    ; 3.51 V              ; -0.0549 V           ; 0.204 V                              ; 0.244 V                              ; 6.37e-10 s                  ; 6.52e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 3.1e-07 V                   ; 3.51 V             ; -0.0549 V          ; 0.204 V                             ; 0.244 V                             ; 6.37e-10 s                 ; 6.52e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[0]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[1]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[2]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[3]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[4]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[5]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[6]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[7]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.57 V              ; -0.0645 V           ; 0.332 V                              ; 0.165 V                              ; 6.78e-10 s                  ; 6.19e-10 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.57 V             ; -0.0645 V          ; 0.332 V                             ; 0.165 V                             ; 6.78e-10 s                 ; 6.19e-10 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[8]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[9]    ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[10]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[11]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[12]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[13]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.48 V              ; -0.0136 V           ; 0.352 V                              ; 0.346 V                              ; 4.12e-09 s                  ; 3.34e-09 s                  ; No                         ; Yes                        ; 3.46 V                      ; 1.29e-07 V                  ; 3.48 V             ; -0.0136 V          ; 0.352 V                             ; 0.346 V                             ; 4.12e-09 s                 ; 3.34e-09 s                 ; No                        ; Yes                       ;
; SDRAM_DQ[14]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
; SDRAM_DQ[15]   ; 3.3-V LVTTL  ; 0 s                 ; 0 s                 ; 3.46 V                       ; 1.29e-07 V                   ; 3.55 V              ; -0.053 V            ; 0.341 V                              ; 0.35 V                               ; 9.04e-10 s                  ; 7.28e-10 s                  ; No                         ; No                         ; 3.46 V                      ; 1.29e-07 V                  ; 3.55 V             ; -0.053 V           ; 0.341 V                             ; 0.35 V                              ; 9.04e-10 s                 ; 7.28e-10 s                 ; No                        ; No                        ;
+----------------+--------------+---------------------+---------------------+------------------------------+------------------------------+---------------------+---------------------+--------------------------------------+--------------------------------------+-----------------------------+-----------------------------+----------------------------+----------------------------+-----------------------------+-----------------------------+--------------------+--------------------+-------------------------------------+-------------------------------------+----------------------------+----------------------------+---------------------------+---------------------------+


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Setup Transfers                                                                                                                                                                                             ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1806     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 10743    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7331     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3782646  ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Hold Transfers                                                                                                                                                                                              ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 1806     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 10743    ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 7331     ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 3782646  ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Recovery Transfers                                                                                                                                                                                          ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2305     ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Removal Transfers                                                                                                                                                                                           ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; From Clock                                                                     ; To Clock                                                                       ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; 146      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 508      ; 0        ; 0        ; 0        ;
; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] ; 2305     ; 0        ; 0        ; 0        ;
+--------------------------------------------------------------------------------+--------------------------------------------------------------------------------+----------+----------+----------+----------+
Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.


---------------
; Report TCCS ;
---------------
No dedicated SERDES Transmitter circuitry present in device or used in design


---------------
; Report RSKM ;
---------------
No dedicated SERDES Receiver circuitry present in device or used in design


+------------------------------------------------+
; Unconstrained Paths                            ;
+---------------------------------+-------+------+
; Property                        ; Setup ; Hold ;
+---------------------------------+-------+------+
; Illegal Clocks                  ; 0     ; 0    ;
; Unconstrained Clocks            ; 0     ; 0    ;
; Unconstrained Input Ports       ; 29    ; 29   ;
; Unconstrained Input Port Paths  ; 61    ; 61   ;
; Unconstrained Output Ports      ; 55    ; 55   ;
; Unconstrained Output Port Paths ; 157   ; 157  ;
+---------------------------------+-------+------+


+------------------------------------+
; TimeQuest Timing Analyzer Messages ;
+------------------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit TimeQuest Timing Analyzer
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Jun 29 12:45:41 2014
Info: Command: quartus_sta atari800core -c atari800core
Info: qsta_default_script.tcl version: #1
Info (11104): Parallel Compilation has detected 4 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 2 of the 2 physical processors detected instead.
Info (21077): Low junction temperature is 0 degrees C
Info (21077): High junction temperature is 85 degrees C
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 11 -multiply_by 63 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 231.43 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info: Found TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS = ON
Info: Analyzing Slow 1200mV 85C Model
Info (332146): Worst-case setup slack is 0.853
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.853         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.790         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.453
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.453         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.454         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 5.551
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.551         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.532         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 2.716
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.716         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.661         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.517
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.517         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.153         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.423         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.862         0.000 FPGA_CLK 
Info: Analyzing Slow 1200mV 0C Model
Info (334003): Started post-fitting delay annotation
Info (334004): Delay annotation completed successfully
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 1.524
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.524         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     3.214         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.402
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.402         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     0.403         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case recovery slack is 6.080
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.080         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     7.871         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 2.430
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     2.430         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     4.223         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.518
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.518         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.114         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.426         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.837         0.000 FPGA_CLK 
Info: Analyzing Fast 1200mV 0C Model
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Info (332146): Worst-case setup slack is 6.959
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     6.959         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     7.644         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case hold slack is 0.187
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     0.187         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     0.187         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case recovery slack is 8.892
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     8.892         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):     9.755         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
Info (332146): Worst-case removal slack is 1.212
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     1.212         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):     2.128         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
Info (332146): Worst-case minimum pulse width slack is 5.605
    Info (332119):     Slack End Point TNS Clock 
    Info (332119): ========= ============= =====================
    Info (332119):     5.605         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    17.206         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1] 
    Info (332119):    17.437         0.000 \gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0] 
    Info (332119):    99.405         0.000 FPGA_CLK 
Info (332102): Design is not fully constrained for setup requirements
Info (332102): Design is not fully constrained for hold requirements
Info: Quartus II 32-bit TimeQuest Timing Analyzer was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 495 megabytes
    Info: Processing ended: Sun Jun 29 12:46:00 2014
    Info: Elapsed time: 00:00:19
    Info: Total CPU time (on all processors): 00:00:23


