Design Assistant report for atari800core
Sun Jun 29 12:46:15 2014
Quartus II 32-bit Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition


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; Table of Contents ;
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  1. Legal Notice
  2. Design Assistant Summary
  3. Design Assistant Settings
  4. High Violations
  5. Medium Violations
  6. Information only Violations
  7. Design Assistant Messages



----------------
; Legal Notice ;
----------------
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+-------------------------------------------------------------------------+
; Design Assistant Summary                                                ;
+-----------------------------------+-------------------------------------+
; Design Assistant Status           ; Analyzed - Sun Jun 29 12:46:15 2014 ;
; Revision Name                     ; atari800core                        ;
; Top-level Entity Name             ; atari800core_mcc                    ;
; Family                            ; Cyclone III                         ;
; Total Critical Violations         ; 0                                   ;
; Total High Violations             ; 320                                 ;
; - Rule R101                       ; 1                                   ;
; - Rule S102                       ; 9                                   ;
; - Rule D101                       ; 256                                 ;
; - Rule D103                       ; 54                                  ;
; Total Medium Violations           ; 9                                   ;
; - Rule R105                       ; 1                                   ;
; - Rule D102                       ; 8                                   ;
; Total Information only Violations ; 194                                 ;
; - Rule T101                       ; 144                                 ;
; - Rule T102                       ; 50                                  ;
+-----------------------------------+-------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Design Assistant Settings                                                                                                                                                                                                                                                                                ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Option                                                                                                                                                                                                                                                                               ; Setting      ; To ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+
; Design Assistant mode                                                                                                                                                                                                                                                                ; Post-Fitting ;    ;
; Threshold value for clock net not mapped to clock spines rule                                                                                                                                                                                                                        ; 25           ;    ;
; Minimum number of clock port feed by gated clocks                                                                                                                                                                                                                                    ; 30           ;    ;
; Minimum number of node fan-out                                                                                                                                                                                                                                                       ; 30           ;    ;
; Maximum number of nodes to report                                                                                                                                                                                                                                                    ; 50           ;    ;
; Rule C101: Gated clock should be implemented according to the Altera standard scheme                                                                                                                                                                                                 ; On           ;    ;
; Rule C102: Logic cell should not be used to generate an inverted clock signal                                                                                                                                                                                                        ; On           ;    ;
; Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power                                                                                                                                                                          ; On           ;    ;
; Rule C104: Clock signal source should drive only clock input ports                                                                                                                                                                                                                   ; On           ;    ;
; Rule C105: Clock signal should be a global signal (Rule applies during post-fitting analysis. This rule applies during both post-fitting analysis and post-synthesis analysis if the design targets a MAX 3000 or MAX 7000 device. For more information, see the Help for the rule.) ; On           ;    ;
; Rule C106: Clock signal source should not drive registers triggered by different clock edges                                                                                                                                                                                         ; On           ;    ;
; Rule R101: Combinational logic used as a reset signal should be synchronized                                                                                                                                                                                                         ; On           ;    ;
; Rule R102: External reset signals should be synchronized using two cascaded registers                                                                                                                                                                                                ; On           ;    ;
; Rule R103: External reset signal should be correctly synchronized                                                                                                                                                                                                                    ; On           ;    ;
; Rule R104: The reset signal that is generated in one clock domain and used in another clock domain should be correctly synchronized                                                                                                                                                  ; On           ;    ;
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized                                                                                                                                                            ; On           ;    ;
; Rule T101: Nodes with more than the specified number of fan-outs                                                                                                                                                                                                                     ; On           ;    ;
; Rule T102: Top nodes with the highest number of fan-outs                                                                                                                                                                                                                             ; On           ;    ;
; Rule A101: Design should not contain combinational loops                                                                                                                                                                                                                             ; On           ;    ;
; Rule A102: Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                           ; On           ;    ;
; Rule A103: Design should not contain delay chains                                                                                                                                                                                                                                    ; On           ;    ;
; Rule A104: Design should not contain ripple clock structures                                                                                                                                                                                                                         ; On           ;    ;
; Rule A105: Pulses should not be implemented asynchronously                                                                                                                                                                                                                           ; On           ;    ;
; Rule A106: Multiple pulses should not be generated in design                                                                                                                                                                                                                         ; On           ;    ;
; Rule A107: Design should not contain SR latches                                                                                                                                                                                                                                      ; On           ;    ;
; Rule A108: Design should not contain latches                                                                                                                                                                                                                                         ; On           ;    ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source                                                                                                                                                                             ; On           ;    ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                                                                                                                                ; On           ;    ;
; Rule S103: More than one asynchronous port of a register should not be driven by the same signal source                                                                                                                                                                              ; On           ;    ;
; Rule S104: Clock port and any other port of a register should not be driven by the same signal source                                                                                                                                                                                ; On           ;    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                        ; On           ;    ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain                                                                                                                 ; On           ;    ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                              ; On           ;    ;
; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains                                                                                                                                                                        ; Off          ;    ;
; Rule M102: No reset signal defined to initialize the state machine                                                                                                                                                                                                                   ; Off          ;    ;
; Rule M103: State machine should not contain an unreachable state                                                                                                                                                                                                                     ; Off          ;    ;
; Rule M104: State machine should not contain a deadlock state                                                                                                                                                                                                                         ; Off          ;    ;
; Rule M105: State machine should not contain a dead transition                                                                                                                                                                                                                        ; Off          ;    ;
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; High Violations                                                                                                                                                                                                                                                                                                                  ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Rule name                                                                                                                                                                    ; Name                                                                                                                                              ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+
; Rule R101: Combinational logic used as a reset signal should be synchronized                                                                                                 ; comb~0                                                                                                                                            ;
;  Reset signal destination node(s) list                                                                                                                                       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|vsync_reg                                                      ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg                                   ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                        ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                         ;
;  Synchronous and reset port source node(s) list                                                                                                                              ; comb~0                                                                                                                                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 1                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]                                           ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[7]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[4]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[5]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[0]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[6]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_bena_reg[1]                                                                                                                                   ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_bena_reg[0]                                                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 2                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 3                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; sdram_reset_n_reg                                                                                                                                 ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 4                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_read_r                                                                                 ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[4]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[0]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[15]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[14]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[13]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[12]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 5                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                             ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[4]                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[17]                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[2]                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[23]                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[13]                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                             ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[8]                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[9]                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|idim_r                                                                                      ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_load2                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 6                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; seq_reg[8]                                                                                                                                        ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; sdram_reset_n_reg                                                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 7                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; seq_reg[7]                                                                                                                                        ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; sdram_reset_n_reg                                                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 8                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_locked"       ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|pll_lock_sync            ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[4]                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[17]                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[2]                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[23]                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|sp_r[13]                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_resync                                                                             ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[7]                            ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_display_list|value_reg[10]       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|pmbase_reg[2]                                                ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[3]                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 9                                                                  ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 10                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 11                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 12                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 13                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 14                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]                                                                                                   ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[10]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 15                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[2]                                                                                   ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[10]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 16                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 17                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; sdram_request_complete_reg                                                                                                                        ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[6]                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[5]                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[4]                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[3]                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[2]                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey2|pokey_countdown_timer:timer1|count_reg[1]                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_ready_reg                                          ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"  ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theCpuCycle.cycleBranchPage           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 18                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[22]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[30]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[2]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[3]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[1]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[21]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[16]                                                                                                                                    ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_refr_req                                                                                                            ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_rd_reg                                                                                                              ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_do_reg[24]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 19                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                                ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[8]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[7]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[6]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                       ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_request_reg                                                                                                                                 ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 20                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]                                                                                                 ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[2]                                                                                                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 21                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]                                                                                                 ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[4]                                                                                                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 22                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]                                                                                                 ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[3]                                                                                                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 23                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[11]                                                                                  ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[11]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 24                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]                                                                                                 ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[5]                                                                                                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 25                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]                                                                                                ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; sdram_ctrl:sdram_controller|r_sdram_addr[1]                                                                                                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 26                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]                                                                                                  ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[12]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 27                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[12]                                                                                  ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[12]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 28                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]                                                                                                   ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[0]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[8]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 29                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[0]                                                                                   ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[0]                                                                                                                                     ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[8]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 30                                                                 ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]                                                                                                  ;
;  Destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"  ; ram_di_reg[13]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 31                                                                 ;                                                                                                                                                   ;
;  Structure 31                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[13]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 32                                                                 ;                                                                                                                                                   ;
;  Structure 32                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[5]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 33                                                                 ;                                                                                                                                                   ;
;  Structure 33                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[5]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 34                                                                 ;                                                                                                                                                   ;
;  Structure 34                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 35                                                                 ;                                                                                                                                                   ;
;  Structure 35                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|write_en_r                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 36                                                                 ;                                                                                                                                                   ;
;  Structure 36                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[1]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 37                                                                 ;                                                                                                                                                   ;
;  Structure 37                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[6]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 38                                                                 ;                                                                                                                                                   ;
;  Structure 38                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[6]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 39                                                                 ;                                                                                                                                                   ;
;  Structure 39                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[2]                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 40                                                                 ;                                                                                                                                                   ;
;  Structure 40                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[3]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 41                                                                 ;                                                                                                                                                   ;
;  Structure 41                                                                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 42                                                                 ;                                                                                                                                                   ;
;  Structure 42                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[6]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 43                                                                 ;                                                                                                                                                   ;
;  Structure 43                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 44                                                                 ;                                                                                                                                                   ;
;  Structure 44                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 45                                                                 ;                                                                                                                                                   ;
;  Structure 45                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 46                                                                 ;                                                                                                                                                   ;
;  Structure 46                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[20]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 47                                                                 ;                                                                                                                                                   ;
;  Structure 47                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[20]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 48                                                                 ;                                                                                                                                                   ;
;  Structure 48                                                                                                                                                                ; ram_do_reg[27]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 49                                                                 ;                                                                                                                                                   ;
;  Structure 49                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_READ_reg                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 50                                                                 ;                                                                                                                                                   ;
;  Structure 50                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[21]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 51                                                                 ;                                                                                                                                                   ;
;  Structure 51                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[21]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 52                                                                 ;                                                                                                                                                   ;
;  Structure 52                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[30]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 53                                                                 ;                                                                                                                                                   ;
;  Structure 53                                                                                                                                                                ; ram_do_reg[19]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 54                                                                 ;                                                                                                                                                   ;
;  Structure 54                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|width_8bit_reg                                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 55                                                                 ;                                                                                                                                                   ;
;  Structure 55                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[1]                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 56                                                                 ;                                                                                                                                                   ;
;  Structure 56                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                                       ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 57                                                                 ;                                                                                                                                                   ;
;  Structure 57                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[0]                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 58                                                                 ;                                                                                                                                                   ;
;  Structure 58                                                                                                                                                                ; ram_do_reg[31]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 59                                                                 ;                                                                                                                                                   ;
;  Structure 59                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[31]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 60                                                                 ;                                                                                                                                                   ;
;  Structure 60                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[31]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 61                                                                 ;                                                                                                                                                   ;
;  Structure 61                                                                                                                                                                ; ram_do_reg[18]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 62                                                                 ;                                                                                                                                                   ;
;  Structure 62                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[10]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 63                                                                 ;                                                                                                                                                   ;
;  Structure 63                                                                                                                                                                ; ram_do_reg[17]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 64                                                                 ;                                                                                                                                                   ;
;  Structure 64                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[17]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 65                                                                 ;                                                                                                                                                   ;
;  Structure 65                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[17]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 66                                                                 ;                                                                                                                                                   ;
;  Structure 66                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[24]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 67                                                                 ;                                                                                                                                                   ;
;  Structure 67                                                                                                                                                                ; ram_do_reg[22]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 68                                                                 ;                                                                                                                                                   ;
;  Structure 68                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[26]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 69                                                                 ;                                                                                                                                                   ;
;  Structure 69                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[26]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 70                                                                 ;                                                                                                                                                   ;
;  Structure 70                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[29]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 71                                                                 ;                                                                                                                                                   ;
;  Structure 71                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[29]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 72                                                                 ;                                                                                                                                                   ;
;  Structure 72                                                                                                                                                                ; ram_do_reg[28]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 73                                                                 ;                                                                                                                                                   ;
;  Structure 73                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[8]                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 74                                                                 ;                                                                                                                                                   ;
;  Structure 74                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[7]                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 75                                                                 ;                                                                                                                                                   ;
;  Structure 75                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[28]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 76                                                                 ;                                                                                                                                                   ;
;  Structure 76                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[28]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 77                                                                 ;                                                                                                                                                   ;
;  Structure 77                                                                                                                                                                ; ram_do_reg[29]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 78                                                                 ;                                                                                                                                                   ;
;  Structure 78                                                                                                                                                                ; ram_do_reg[26]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 79                                                                 ;                                                                                                                                                   ;
;  Structure 79                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[9]                                                                                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 80                                                                 ;                                                                                                                                                   ;
;  Structure 80                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[22]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 81                                                                 ;                                                                                                                                                   ;
;  Structure 81                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[22]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 82                                                                 ;                                                                                                                                                   ;
;  Structure 82                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[24]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 83                                                                 ;                                                                                                                                                   ;
;  Structure 83                                                                                                                                                                ; ram_do_reg[24]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 84                                                                 ;                                                                                                                                                   ;
;  Structure 84                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[18]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 85                                                                 ;                                                                                                                                                   ;
;  Structure 85                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[18]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 86                                                                 ;                                                                                                                                                   ;
;  Structure 86                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[3]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 87                                                                 ;                                                                                                                                                   ;
;  Structure 87                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[3]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 88                                                                 ;                                                                                                                                                   ;
;  Structure 88                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[4]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 89                                                                 ;                                                                                                                                                   ;
;  Structure 89                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[4]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 90                                                                 ;                                                                                                                                                   ;
;  Structure 90                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[7]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 91                                                                 ;                                                                                                                                                   ;
;  Structure 91                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[7]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 92                                                                 ;                                                                                                                                                   ;
;  Structure 92                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[8]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 93                                                                 ;                                                                                                                                                   ;
;  Structure 93                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[8]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 94                                                                 ;                                                                                                                                                   ;
;  Structure 94                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[9]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 95                                                                 ;                                                                                                                                                   ;
;  Structure 95                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[9]                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 96                                                                 ;                                                                                                                                                   ;
;  Structure 96                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[25]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 97                                                                 ;                                                                                                                                                   ;
;  Structure 97                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[25]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 98                                                                 ;                                                                                                                                                   ;
;  Structure 98                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[10]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 99                                                                 ;                                                                                                                                                   ;
;  Structure 99                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[10]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 100                                                                ;                                                                                                                                                   ;
;  Structure 100                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[27]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 101                                                                ;                                                                                                                                                   ;
;  Structure 101                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[27]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 102                                                                ;                                                                                                                                                   ;
;  Structure 102                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[11]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 103                                                                ;                                                                                                                                                   ;
;  Structure 103                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[19]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 104                                                                ;                                                                                                                                                   ;
;  Structure 104                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[19]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 105                                                                ;                                                                                                                                                   ;
;  Structure 105                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[12]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 106                                                                ;                                                                                                                                                   ;
;  Structure 106                                                                                                                                                               ; ram_do_reg[30]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 107                                                                ;                                                                                                                                                   ;
;  Structure 107                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[30]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 108                                                                ;                                                                                                                                                   ;
;  Structure 108                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[14]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 109                                                                ;                                                                                                                                                   ;
;  Structure 109                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[14]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 110                                                                ;                                                                                                                                                   ;
;  Structure 110                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[15]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 111                                                                ;                                                                                                                                                   ;
;  Structure 111                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[15]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 112                                                                ;                                                                                                                                                   ;
;  Structure 112                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[16]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 113                                                                ;                                                                                                                                                   ;
;  Structure 113                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[16]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 114                                                                ;                                                                                                                                                   ;
;  Structure 114                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[23]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 115                                                                ;                                                                                                                                                   ;
;  Structure 115                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[23]                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 116                                                                ;                                                                                                                                                   ;
;  Structure 116                                                                                                                                                               ; ram_do_reg[16]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 117                                                                ;                                                                                                                                                   ;
;  Structure 117                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[16]                                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 118                                                                ;                                                                                                                                                   ;
;  Structure 118                                                                                                                                                               ; ram_do_reg[21]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 119                                                                ;                                                                                                                                                   ;
;  Structure 119                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|read_en_r                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 120                                                                ;                                                                                                                                                   ;
;  Structure 120                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|theWe                                 ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 121                                                                ;                                                                                                                                                   ;
;  Structure 121                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[2]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 122                                                                ;                                                                                                                                                   ;
;  Structure 122                                                                                                                                                               ; ram_do_reg[1]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 123                                                                ;                                                                                                                                                   ;
;  Structure 123                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 124                                                                ;                                                                                                                                                   ;
;  Structure 124                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 125                                                                ;                                                                                                                                                   ;
;  Structure 125                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 126                                                                ;                                                                                                                                                   ;
;  Structure 126                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 127                                                                ;                                                                                                                                                   ;
;  Structure 127                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[11]                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 128                                                                ;                                                                                                                                                   ;
;  Structure 128                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[10]                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 129                                                                ;                                                                                                                                                   ;
;  Structure 129                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[0]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 130                                                                ;                                                                                                                                                   ;
;  Structure 130                                                                                                                                                               ; ram_do_reg[3]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 131                                                                ;                                                                                                                                                   ;
;  Structure 131                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 132                                                                ;                                                                                                                                                   ;
;  Structure 132                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[9]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 133                                                                ;                                                                                                                                                   ;
;  Structure 133                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[1]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 134                                                                ;                                                                                                                                                   ;
;  Structure 134                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 135                                                                ;                                                                                                                                                   ;
;  Structure 135                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 136                                                                ;                                                                                                                                                   ;
;  Structure 136                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[3]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 137                                                                ;                                                                                                                                                   ;
;  Structure 137                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[3]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 138                                                                ;                                                                                                                                                   ;
;  Structure 138                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 139                                                                ;                                                                                                                                                   ;
;  Structure 139                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[8]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 140                                                                ;                                                                                                                                                   ;
;  Structure 140                                                                                                                                                               ; ram_do_reg[6]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 141                                                                ;                                                                                                                                                   ;
;  Structure 141                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[1]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 142                                                                ;                                                                                                                                                   ;
;  Structure 142                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[0]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 143                                                                ;                                                                                                                                                   ;
;  Structure 143                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[1]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 144                                                                ;                                                                                                                                                   ;
;  Structure 144                                                                                                                                                               ; ram_do_reg[0]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 145                                                                ;                                                                                                                                                   ;
;  Structure 145                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[2]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 146                                                                ;                                                                                                                                                   ;
;  Structure 146                                                                                                                                                               ; ram_do_reg[5]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 147                                                                ;                                                                                                                                                   ;
;  Structure 147                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[4]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 148                                                                ;                                                                                                                                                   ;
;  Structure 148                                                                                                                                                               ; ram_do_reg[4]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 149                                                                ;                                                                                                                                                   ;
;  Structure 149                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[12]                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 150                                                                ;                                                                                                                                                   ;
;  Structure 150                                                                                                                                                               ; ram_do_reg[7]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 151                                                                ;                                                                                                                                                   ;
;  Structure 151                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[2]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 152                                                                ;                                                                                                                                                   ;
;  Structure 152                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 153                                                                ;                                                                                                                                                   ;
;  Structure 153                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 154                                                                ;                                                                                                                                                   ;
;  Structure 154                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[13]                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 155                                                                ;                                                                                                                                                   ;
;  Structure 155                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 156                                                                ;                                                                                                                                                   ;
;  Structure 156                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 157                                                                ;                                                                                                                                                   ;
;  Structure 157                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[2]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 158                                                                ;                                                                                                                                                   ;
;  Structure 158                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[15]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 159                                                                ;                                                                                                                                                   ;
;  Structure 159                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[15]                            ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 160                                                                ;                                                                                                                                                   ;
;  Structure 160                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 161                                                                ;                                                                                                                                                   ;
;  Structure 161                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[7]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 162                                                                ;                                                                                                                                                   ;
;  Structure 162                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[7]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 163                                                                ;                                                                                                                                                   ;
;  Structure 163                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[7]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 164                                                                ;                                                                                                                                                   ;
;  Structure 164                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 165                                                                ;                                                                                                                                                   ;
;  Structure 165                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[13]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 166                                                                ;                                                                                                                                                   ;
;  Structure 166                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[5]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 167                                                                ;                                                                                                                                                   ;
;  Structure 167                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[5]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 168                                                                ;                                                                                                                                                   ;
;  Structure 168                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[5]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 169                                                                ;                                                                                                                                                   ;
;  Structure 169                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 170                                                                ;                                                                                                                                                   ;
;  Structure 170                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[4]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 171                                                                ;                                                                                                                                                   ;
;  Structure 171                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[6]                             ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 172                                                                ;                                                                                                                                                   ;
;  Structure 172                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[4]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 173                                                                ;                                                                                                                                                   ;
;  Structure 173                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|doReg[3]                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 174                                                                ;                                                                                                                                                   ;
;  Structure 174                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[3]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 175                                                                ;                                                                                                                                                   ;
;  Structure 175                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[2]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 176                                                                ;                                                                                                                                                   ;
;  Structure 176                                                                                                                                                               ; ram_do_reg[2]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 177                                                                ;                                                                                                                                                   ;
;  Structure 177                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[1]                                                                                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 178                                                                ;                                                                                                                                                   ;
;  Structure 178                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[1]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 179                                                                ;                                                                                                                                                   ;
;  Structure 179                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[0]                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 180                                                                ;                                                                                                                                                   ;
;  Structure 180                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[0]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 181                                                                ;                                                                                                                                                   ;
;  Structure 181                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[0]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 182                                                                ;                                                                                                                                                   ;
;  Structure 182                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[8]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 183                                                                ;                                                                                                                                                   ;
;  Structure 183                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[7]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 184                                                                ;                                                                                                                                                   ;
;  Structure 184                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[7]                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 185                                                                ;                                                                                                                                                   ;
;  Structure 185                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[1]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 186                                                                ;                                                                                                                                                   ;
;  Structure 186                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 187                                                                ;                                                                                                                                                   ;
;  Structure 187                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[9]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 188                                                                ;                                                                                                                                                   ;
;  Structure 188                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[4]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 189                                                                ;                                                                                                                                                   ;
;  Structure 189                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 190                                                                ;                                                                                                                                                   ;
;  Structure 190                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[10]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 191                                                                ;                                                                                                                                                   ;
;  Structure 191                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[11]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 192                                                                ;                                                                                                                                                   ;
;  Structure 192                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[12]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 193                                                                ;                                                                                                                                                   ;
;  Structure 193                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 194                                                                ;                                                                                                                                                   ;
;  Structure 194                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[12]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 195                                                                ;                                                                                                                                                   ;
;  Structure 195                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 196                                                                ;                                                                                                                                                   ;
;  Structure 196                                                                                                                                                               ; ram_do_reg[20]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 197                                                                ;                                                                                                                                                   ;
;  Structure 197                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 198                                                                ;                                                                                                                                                   ;
;  Structure 198                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[6]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 199                                                                ;                                                                                                                                                   ;
;  Structure 199                                                                                                                                                               ; ram_do_reg[15]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 200                                                                ;                                                                                                                                                   ;
;  Structure 200                                                                                                                                                               ; ram_do_reg[14]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 201                                                                ;                                                                                                                                                   ;
;  Structure 201                                                                                                                                                               ; ram_do_reg[11]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 202                                                                ;                                                                                                                                                   ;
;  Structure 202                                                                                                                                                               ; ram_do_reg[9]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 203                                                                ;                                                                                                                                                   ;
;  Structure 203                                                                                                                                                               ; ram_do_reg[13]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 204                                                                ;                                                                                                                                                   ;
;  Structure 204                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[13]                                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 205                                                                ;                                                                                                                                                   ;
;  Structure 205                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                                                                               ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 206                                                                ;                                                                                                                                                   ;
;  Structure 206                                                                                                                                                               ; ram_do_reg[10]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 207                                                                ;                                                                                                                                                   ;
;  Structure 207                                                                                                                                                               ; ram_do_reg[12]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 208                                                                ;                                                                                                                                                   ;
;  Structure 208                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[12]                                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 209                                                                ;                                                                                                                                                   ;
;  Structure 209                                                                                                                                                               ; ram_do_reg[25]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 210                                                                ;                                                                                                                                                   ;
;  Structure 210                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                                               ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 211                                                                ;                                                                                                                                                   ;
;  Structure 211                                                                                                                                                               ; ram_do_reg[8]                                                                                                                                     ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 212                                                                ;                                                                                                                                                   ;
;  Structure 212                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[11]                                                                                                  ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 213                                                                ;                                                                                                                                                   ;
;  Structure 213                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[11]                                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 214                                                                ;                                                                                                                                                   ;
;  Structure 214                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[4]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 215                                                                ;                                                                                                                                                   ;
;  Structure 215                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 216                                                                ;                                                                                                                                                   ;
;  Structure 216                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[14]                                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 217                                                                ;                                                                                                                                                   ;
;  Structure 217                                                                                                                                                               ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[15]                                                                                              ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 218                                                                ;                                                                                                                                                   ;
;  Structure 218                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 219                                                                ;                                                                                                                                                   ;
;  Structure 219                                                                                                                                                               ; ram_do_reg[23]                                                                                                                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 220                                                                ;                                                                                                                                                   ;
;  Structure 220                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 221                                                                ;                                                                                                                                                   ;
;  Structure 221                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 222                                                                ;                                                                                                                                                   ;
;  Structure 222                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 223                                                                ;                                                                                                                                                   ;
;  Structure 223                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[16]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 224                                                                ;                                                                                                                                                   ;
;  Structure 224                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 225                                                                ;                                                                                                                                                   ;
;  Structure 225                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[5]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 226                                                                ;                                                                                                                                                   ;
;  Structure 226                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[5]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 227                                                                ;                                                                                                                                                   ;
;  Structure 227                                                                                                                                                               ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[17]                                                                                                ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 228                                                                ;                                                                                                                                                   ;
;  Structure 228                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]                                         ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 229                                                                ;                                                                                                                                                   ;
;  Structure 229                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[6]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 230                                                                ;                                                                                                                                                   ;
;  Structure 230                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[6]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 231                                                                ;                                                                                                                                                   ;
;  Structure 231                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[7]                                          ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 232                                                                ;                                                                                                                                                   ;
;  Structure 232                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[7]                                           ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 233                                                                ;                                                                                                                                                   ;
;  Structure 233                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[16]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 234                                                                ;                                                                                                                                                   ;
;  Structure 234                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[17]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 235                                                                ;                                                                                                                                                   ;
;  Structure 235                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[18]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 236                                                                ;                                                                                                                                                   ;
;  Structure 236                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[19]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 237                                                                ;                                                                                                                                                   ;
;  Structure 237                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[20]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 238                                                                ;                                                                                                                                                   ;
;  Structure 238                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[21]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 239                                                                ;                                                                                                                                                   ;
;  Structure 239                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[22]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 240                                                                ;                                                                                                                                                   ;
;  Structure 240                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[23]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 241                                                                ;                                                                                                                                                   ;
;  Structure 241                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[24]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 242                                                                ;                                                                                                                                                   ;
;  Structure 242                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[8]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 243                                                                ;                                                                                                                                                   ;
;  Structure 243                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[9]                                    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 244                                                                ;                                                                                                                                                   ;
;  Structure 244                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[25]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 245                                                                ;                                                                                                                                                   ;
;  Structure 245                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[10]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 246                                                                ;                                                                                                                                                   ;
;  Structure 246                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[26]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 247                                                                ;                                                                                                                                                   ;
;  Structure 247                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[11]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 248                                                                ;                                                                                                                                                   ;
;  Structure 248                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[27]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 249                                                                ;                                                                                                                                                   ;
;  Structure 249                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[12]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 250                                                                ;                                                                                                                                                   ;
;  Structure 250                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[28]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 251                                                                ;                                                                                                                                                   ;
;  Structure 251                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[29]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 252                                                                ;                                                                                                                                                   ;
;  Structure 252                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[13]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 253                                                                ;                                                                                                                                                   ;
;  Structure 253                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[14]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 254                                                                ;                                                                                                                                                   ;
;  Structure 254                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[30]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 255                                                                ;                                                                                                                                                   ;
;  Structure 255                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[15]                                   ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains - Structure 256                                                                ;                                                                                                                                                   ;
;  Structure 256                                                                                                                                                               ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|DATA_WRITE_reg[31]                                   ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 1                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 2                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; sdram_reset_n_reg                                                                                                                                 ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 3                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; sdram_ctrl:sdram_controller|sdram_rdy                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_write_r                                                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_8BIT_WRITE_ENABLE_reg                                                                                       ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 4                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_locked"       ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|pll_lock_sync            ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[2]                                            ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[31][1]                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|chbase_raw_reg[1]                                            ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|wide_delay_line:chbase_delay|shift_reg[31][0]                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[7]                                               ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][7]                    ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|sizem_raw_reg[6]                                               ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:sizem_delay|shift_reg[3][6]                    ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hposm3_raw_reg[5]                                              ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|wide_delay_line:hposm3_delay|shift_reg[4][5]                   ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 5                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 6                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 7                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg                                           ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 8                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 9                                                        ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]                                  ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 10                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 11                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 12                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]                                                                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 13                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]                                                                                               ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 14                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]                                                                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 15                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]                                         ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 16                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]                                                                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 17                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; ram_do_reg[1]                                                                                                                                     ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[1]                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[1]                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 18                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]                                         ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 19                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]                                                                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 20                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]                                         ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 21                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]                                                                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 22                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; ram_do_reg[3]                                                                                                                                     ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[3]                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[3]                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 23                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]                                          ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 24                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]                                          ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 25                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; ram_do_reg[6]                                                                                                                                     ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[6]                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[14]        ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[6]                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 26                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; ram_do_reg[0]                                                                                                                                     ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[0]                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[0]                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 27                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; ram_do_reg[5]                                                                                                                                     ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[5]                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[13]        ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[5]                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 28                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; ram_do_reg[4]                                                                                                                                     ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[4]                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[4]                         ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[12]        ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 29                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]"       ; ram_do_reg[7]                                                                                                                                     ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg[7]                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|antic_counter:antic_counter_memory_scan|value_reg[15]        ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|display_list_address_low_temp_reg[7]                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 30                                                       ;                                                                                                                                                   ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]"       ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]                                                                                                ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_psel_dly[0]                                                                                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 31                                                       ;                                                                                                                                                   ;
;  Structure 31                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|myAddr[14]                            ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 32                                                       ;                                                                                                                                                   ;
;  Structure 32                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[14]                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 33                                                       ;                                                                                                                                                   ;
;  Structure 33                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[14]                                          ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 34                                                       ;                                                                                                                                                   ;
;  Structure 34                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[15]                                          ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 35                                                       ;                                                                                                                                                   ;
;  Structure 35                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[15]                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 36                                                       ;                                                                                                                                                   ;
;  Structure 36                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[13]                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 37                                                       ;                                                                                                                                                   ;
;  Structure 37                                                                                                                                                                ; ram_do_reg[2]                                                                                                                                     ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 38                                                       ;                                                                                                                                                   ;
;  Structure 38                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[0]                                              ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 39                                                       ;                                                                                                                                                   ;
;  Structure 39                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[0]                                           ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 40                                                       ;                                                                                                                                                   ;
;  Structure 40                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[7]                                           ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 41                                                       ;                                                                                                                                                   ;
;  Structure 41                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[7]                                              ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 42                                                       ;                                                                                                                                                   ;
;  Structure 42                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg[1]                                           ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 43                                                       ;                                                                                                                                                   ;
;  Structure 43                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg[1]                                              ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 44                                                       ;                                                                                                                                                   ;
;  Structure 44                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[10]                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 45                                                       ;                                                                                                                                                   ;
;  Structure 45                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[11]                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 46                                                       ;                                                                                                                                                   ;
;  Structure 46                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|write_enable_reg                                     ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 47                                                       ;                                                                                                                                                   ;
;  Structure 47                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 48                                                       ;                                                                                                                                                   ;
;  Structure 48                                                                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[9]                                                                                               ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 49                                                       ;                                                                                                                                                   ;
;  Structure 49                                                                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[8]                                                                                               ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 50                                                       ;                                                                                                                                                   ;
;  Structure 50                                                                                                                                                                ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[10]                                                                                              ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 51                                                       ;                                                                                                                                                   ;
;  Structure 51                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]                                         ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 52                                                       ;                                                                                                                                                   ;
;  Structure 52                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|cpu_extra_enable_reg                                ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 53                                                       ;                                                                                                                                                   ;
;  Structure 53                                                                                                                                                                ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[20]                                                                                                ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains - Structure 54                                                       ;                                                                                                                                                   ;
;  Structure 54                                                                                                                                                                ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]                                         ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Medium Violations                                                                                                                                                                                                                                                                                 ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+
; Rule name                                                                                                                                                                                ; Name                                                                                                   ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+
; Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized                                                                ; sdram_reset_ctrl_n_reg                                                                                 ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|sdram_rdy                                                                  ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_init_tmr[10]                                                             ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; sdram_ctrl:sdram_controller|r_init_fsm[2]                                                              ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; seq_reg[11]                                                                                            ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; seq_reg[10]                                                                                            ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; seq_reg[9]                                                                                             ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; seq_reg[8]                                                                                             ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; seq_reg[7]                                                                                             ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; seq_reg[6]                                                                                             ;
;  Reset signal destination node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" ; seq_reg[5]                                                                                             ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 1       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)     ; sdram_ctrl:sdram_controller|r_psel                                                                     ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 2       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)           ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg                                                         ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)     ; sdram_ctrl:sdram_controller|r_psel                                                                     ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 3       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)           ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg                                                       ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)     ; sdram_ctrl:sdram_controller|r_psel                                                                     ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 4       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg  ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)     ; sdram_ctrl:sdram_controller|r_psel                                                                     ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 5       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)           ; ram_do_reg                                                                                             ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)     ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_cache_reg     ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 6       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg   ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)     ; sdram_ctrl:sdram_controller|r_psel                                                                     ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 7       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg      ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)     ; sdram_ctrl:sdram_controller|r_psel                                                                     ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain - Structure 8       ;                                                                                                        ;
;  Source node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]" - (Bus)           ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg   ;
;  Synchronizer node(s) from clock "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]" - (Bus)     ; sdram_ctrl:sdram_controller|r_psel                                                                     ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Information only Violations                                                                                                                                                                                                    ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Rule name                                                        ; Name                                                                                                                                              ; Fan-Out ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------+
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                  ; 62      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|Mux4~2                                                       ; 90      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux125~0                                             ; 97      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux24~1                                              ; 43      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_next[0]~0                                             ; 640     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~0clkctrl                                                                                                                                     ; 2305    ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~0                                                                                                                                            ; 67      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]~0                                                                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux35~0                                                                                                         ; 85      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|memORY_ACCESS                                                                                                   ; 60      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute                                                                            ; 127     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~1                                                                                                                                            ; 140     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; sdram_reset_ctrl_n_reg~clkctrl                                                                                                                    ; 146     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|locked~clkctrl           ; 281     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]~clkctrl ; 4882    ;
; Rule T101: Nodes with more than the specified number of fan-outs ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]~clkctrl ; 146     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0                                                                                                         ; 115     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]                                         ; 61      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]                                                ; 53      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]                                                ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]                                                ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]                                                ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; 61      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; comb~1clkctrl                                                                                                                                     ; 508     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_store_sp                                                                           ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn~48                                                                                     ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[0]~1                                                                            ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164                                                                                   ; 143     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]                                                                                                   ; 60      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg                                                                                    ; 54      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg                                            ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; sdram_ctrl:sdram_controller|r_psel[0]                                                                                                             ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                              ; 61      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]~14                                                                           ; 49      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~0                                                                                      ; 79      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[0]                                                                                     ; 72      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|mult_res1_r[0]~15                                                                           ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|b_r[21]~31                                                                                  ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~2                                                                                      ; 44      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[1]                                                                                     ; 72      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Selector95~1                                                                                ; 46      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux34~0                                                                                                         ; 87      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out4_reg[0]~0                                                                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux32~0                                                                                                         ; 50      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux121~2                                             ; 130     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux33~0                                                                                                         ; 58      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_or                                                                                 ; 37      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux31~0                                                                                                         ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[12]                                                                             ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out3_reg[0]~0                                                                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                                                                     ; 68      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_lshr                                                                               ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                                                                   ; 70      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|out2_reg[0]~0                                                                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|key_value_reg[9]                                                                             ; 71      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|key_value_reg[3]                                                                             ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|key_value_reg[0]                                                                             ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[4]                                                                              ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~34                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]~1                                                ; 148     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|CPU_ENABLE_RDY                                                ; 53      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux102~1                                             ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_and                                                                                ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[20]                                                                             ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|state                                                                              ; 53      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|busy                                                                               ; 51      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                               ; 66      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_out                                                ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~16                                                                                                ; 111     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_im                                                                                 ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_flip                                                                               ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_shift                                                                              ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[28]                                                                             ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_not                                                                                ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_sub                                                                                ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|Equal1~10                                                                          ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|spi_master:spi_master1|count[30]~2                                                                        ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[16]~0                         ; 43      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux123~3                                             ; 115     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[5]~0     ; 45      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[4]~0     ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[3]~0     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux116~2                                             ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux124~0                                             ; 69      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux23~1                                              ; 49      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[7]~1     ; 39      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[1]                                          ; 54      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[0]                                          ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux122~3                                             ; 123     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[1]~2     ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[6]~1     ; 47      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]~4                                                 ; 146     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]~0                                                 ; 158     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|nextOpcInfo[41]~1                     ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[2]~0     ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|complete_address_decoder:decode_addr1|addr_decoded[14]~28    ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]~5                                                 ; 152     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|\calcNextOpcode:myNextOpcode[5]~1     ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]~6                                                 ; 152     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[40]                           ; 38      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[39]                           ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|cpu:cpu6502|cpu_65xx:cpu_6502_peter|opcInfo[38]                           ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux111~2                                             ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]~0                                                ; 144     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]~2                                                 ; 148     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|pokey:pokey1|serial_reset~1                                                                               ; 36      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|complete_address_decoder:decode_addr1|addr_decoded[15]~27    ; 62      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|POKEY_WR_ENABLE~1                                    ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|serial_reset~0                                               ; 60      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcpu_enable~0                                     ; 132     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]~1                                                 ; 149     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hitclr_write~0                                                 ; 62      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|Mux4~1                                                       ; 40      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[0]        ; 110     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[1]        ; 139     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[2]        ; 108     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]        ; 146     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[5]        ; 35      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[5]~3                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[6]~2                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[7]~8                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[3]~6                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[2]~5                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[1]~4                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[0]~1                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|line_buffer_data_in[4]~7                                     ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~36                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~37                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~26                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~39                                                                                                ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~43                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~46                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~51                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~53                                                                                                ; 48      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~55                                                                                                ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[1]                                                                                                   ; 31      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[22]~35                                                                                          ; 32      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; zpucore:zpu|zpu_config_regs:config_regs|pause_reg[22]~34                                                                                          ; 33      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]                                                  ; 91      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1]                                                  ; 79      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[2]                                                  ; 59      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]                                                  ; 86      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]                                                  ; 86      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[7]                                                  ; 55      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]~clkctrl ; 4882    ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~0clkctrl                                                                                                                                     ; 2305    ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_next[0]~0                                             ; 640     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~1clkctrl                                                                                                                                     ; 508     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|locked~clkctrl           ; 281     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]~0                                                 ; 158     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]~5                                                 ; 152     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]~6                                                 ; 152     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]~1                                                 ; 149     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]~2                                                 ; 148     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]~1                                                ; 148     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]~clkctrl ; 146     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]~4                                                 ; 146     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; sdram_reset_ctrl_n_reg~clkctrl                                                                                                                    ; 146     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]        ; 146     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]~0                                                ; 144     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164                                                                                   ; 143     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~1                                                                                                                                            ; 140     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[1]        ; 139     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcpu_enable~0                                     ; 132     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux121~2                                             ; 130     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute                                                                            ; 127     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux122~3                                             ; 123     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux123~3                                             ; 115     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0                                                                                                         ; 115     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~16                                                                                                ; 111     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[0]        ; 110     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[2]        ; 108     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux125~0                                             ; 97      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]                                                  ; 91      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|Mux4~2                                                       ; 90      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux34~0                                                                                                         ; 87      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[6]                                                  ; 86      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[5]                                                  ; 86      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|Mux35~0                                                                                                         ; 85      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[1]                                                  ; 79      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|Add2~0                                                                                      ; 79      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[0]                                                                                     ; 72      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|pc_r[1]                                                                                     ; 72      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; ps2_to_atari800:keyboard_map1|ps2_keyboard:keyboard1|key_value_reg[9]                                                                             ; 71      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[0]                                                                                                   ; 70      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux124~0                                             ; 69      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; enable_divider:enable_179_clock_div_zpu_pokey|enabled_out_reg                                                                                     ; 68      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; comb~0                                                                                                                                            ; 67      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_config_regs:config_regs|spi_dma_reg                                                                                               ; 66      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pokey:pokey1|complete_address_decoder:decode_addr1|addr_decoded[15]~27    ; 62      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]                                                  ; 62      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|hitclr_write~0                                                 ; 62      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_mult5                                                                              ; 61      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]                                         ; 61      ;
+------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------+---------+


+---------------------------+
; Design Assistant Messages ;
+---------------------------+
Info: *******************************************************************
Info: Running Quartus II 32-bit Design Assistant
    Info: Version 13.0.1 Build 232 06/12/2013 Service Pack 1 SJ Web Edition
    Info: Processing started: Sun Jun 29 12:46:06 2014
Info: Command: quartus_drc --read_settings_files=off --write_settings_files=off atari800core -c atari800core
Info (332104): Reading SDC File: 'atari800core.sdc'
Info (332110): Deriving PLL clocks
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|inclk[0]} -divide_by 11 -multiply_by 63 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[0]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[1]}
    Info (332110): create_generated_clock -source {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|inclk[0]} -multiply_by 3 -phase 231.43 -duty_cycle 50.00 -name {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]} {\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll_component|auto_generated|pll1|clk[2]}
Info (332151): Clock uncertainty is not calculated until you update the timing netlist.
Info (332123): Deriving Clock Uncertainty. Please refer to report_sdc in TimeQuest to see clock uncertainties.
Critical Warning (308024): (High) Rule R101: Combinational logic used as a reset signal should be synchronized. Found 1 node(s) related to this rule.
    Critical Warning (308012): Node  "comb~0"
Critical Warning (308074): (High) Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source. Found 9 node(s) related to this rule.
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[21]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[18]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|cpu_fetch_real_reg"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[20]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[16]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[17]"
Critical Warning (308060): (High) Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 256 asynchronous clock domain interface structure(s) related to this rule.
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg[0]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg"
    Critical Warning (308012): Node  "sdram_reset_n_reg"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|byte_read_r"
    Critical Warning (308012): Node  "sdram_ctrl:sdram_controller|sdram_rdy"
    Critical Warning (308012): Node  "seq_reg[8]"
    Critical Warning (308012): Node  "seq_reg[7]"
    Critical Warning (308012): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|pll_lock_sync"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[2]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[2]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg"
    Critical Warning (308012): Node  "sdram_request_complete_reg"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[3]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[5]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[4]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[11]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[6]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[13]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[12]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[12]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[0]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|data_o[0]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPU_DO_reg[13]"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Critical Warning (308067): (High) Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains. (Value defined:2). Found 54 asynchronous clock domain interface structure(s) related to this rule.
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|enable_divider:enable_179_clock_div|enabled_out_reg"
    Critical Warning (308012): Node  "sdram_reset_n_reg"
    Critical Warning (308012): Node  "sdram_ctrl:sdram_controller|sdram_rdy"
    Critical Warning (308012): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|pll_lock_sync"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_fetch_reg"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|allow_real_dma_reg"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|speed_shift_reg[0]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|refresh_fetch_reg"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[18]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[23]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[23]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[21]"
    Critical Warning (308012): Node  "ram_do_reg[1]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[22]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[22]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[19]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[19]"
    Critical Warning (308012): Node  "ram_do_reg[3]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[9]"
    Critical Warning (308012): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg[8]"
    Critical Warning (308012): Node  "ram_do_reg[6]"
    Critical Warning (308012): Node  "ram_do_reg[0]"
    Critical Warning (308012): Node  "ram_do_reg[5]"
    Critical Warning (308012): Node  "ram_do_reg[4]"
    Critical Warning (308012): Node  "ram_do_reg[7]"
    Critical Warning (308012): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg[14]"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Warning (308027): (Medium) Rule R105: The reset signal that is generated in one clock domain and used in another clock domain should be synchronized. Found 1 node(s) related to this rule.
    Warning (308010): Node  "sdram_reset_ctrl_n_reg"
Warning (308071): (Medium) Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain. (Value defined:2). Found 8 asynchronous clock domain interface structure(s) related to this rule.
    Warning (308010): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg (Bus)"
    Warning (308010): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_addr_reg (Bus)"
    Warning (308010): Node  "zpucore:zpu|zpu_config_regs:config_regs|out1_reg (Bus)"
    Warning (308010): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|ADDR_reg (Bus)"
    Warning (308010): Node  "ram_do_reg (Bus)"
    Warning (308010): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|dma_address_reg (Bus)"
    Warning (308010): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_output_reg (Bus)"
    Warning (308010): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|pia:pia1|portb_direction_reg (Bus)"
Info (308046): (Information) Rule T101: Nodes with more than the specified number of fan-outs. (Value defined:30). Found 144 node(s) with highest fan-out.
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[0]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|Mux4~2"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux125~0"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux24~1"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_next[0]~0"
    Info (308011): Node  "comb~0clkctrl"
    Info (308011): Node  "comb~0"
    Info (308011): Node  "zpucore:zpu|zpu_config_regs:config_regs|out1_reg[0]~0"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|Mux35~0"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|memORY_ACCESS"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute"
    Info (308011): Node  "comb~1"
    Info (308011): Node  "sdram_reset_ctrl_n_reg~clkctrl"
    Info (308011): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|locked~clkctrl"
    Info (308011): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]~clkctrl"
    Info (308011): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]~clkctrl"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[1]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[2]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[3]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[1]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_reg[7]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|state_reg[0]"
    Info (308011): Node  "comb~1clkctrl"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn.dec_store_sp"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insn~48"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|fetched_w_r[0]~1"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|result_reg[2]"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_memory_fetch_pending_reg"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308044): (Information) Rule T102: Top nodes with the highest number of fan-outs. (Value defined:50). Found 50 node(s) with highest fan-out.
    Info (308011): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[1]~clkctrl"
    Info (308011): Node  "comb~0clkctrl"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|hcount_next[0]~0"
    Info (308011): Node  "comb~1clkctrl"
    Info (308011): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|locked~clkctrl"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[1]~0"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[2]~5"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[4]~6"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[3]~1"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[5]~2"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[6]~1"
    Info (308011): Node  "pll_downstream_ntsc:\gen_real_pll:gen_tv_ntsc:mcc_pll2|altpll:altpll_component|pll_downstream_ntsc_altpll:auto_generated|wire_pll1_clk[0]~clkctrl"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafm_reg[0]~4"
    Info (308011): Node  "sdram_reset_ctrl_n_reg~clkctrl"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[3]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|grafp0_reg[7]~0"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|insns~164"
    Info (308011): Node  "comb~1"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[1]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|shared_enable:enables|oldcpu_enable~0"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux121~2"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|ZPUMediumCore:myzpu|state.st_execute"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux122~3"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux123~3"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|Mux13~0"
    Info (308011): Node  "zpucore:zpu|zpu_glue:zpu_and_glue|zpu_di_reg[9]~16"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[0]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|antic:antic1|simple_counter:antic_counter_line_buffer|value_reg[2]"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|address_decoder:mmu1|Mux125~0"
    Info (308011): Node  "atari800core_simple_sdram:atarixl_simple_sdram1|atari800core:atari800xl|gtia:gtia1|COLOUR_REG[4]"
    Info (308002): Truncated list of Design Assistant messages to 30 messages. Go to sections under Design Assistant section of Compilation Report for complete lists of Design Assistant messages generated.
Info (308007): Design Assistant information: finished post-fitting analysis of current design -- generated 194 information messages and 329 warning messages
Info: Quartus II 32-bit Design Assistant was successful. 0 errors, 85 warnings
    Info: Peak virtual memory: 369 megabytes
    Info: Processing ended: Sun Jun 29 12:46:15 2014
    Info: Elapsed time: 00:00:09
    Info: Total CPU time (on all processors): 00:00:09


