/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, the Altera Quartus II License Agreement,
the Altera MegaCore Function License Agreement, or other 
applicable license agreement, including, without limitation, 
that your use is for the sole purpose of programming logic 
devices manufactured by Altera and sold by Altera or its 
authorized distributors.  Please refer to the applicable 
agreement for further details.
*/
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(symbol
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	(text "inst" (rect 8 168 20 180)(font "Arial" ))
	(port
		(pt 0 72)
		(input)
		(text "refclk" (rect 0 0 22 12)(font "Arial" (font_size 8)))
		(text "refclk" (rect 4 61 40 72)(font "Arial" (font_size 8)))
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	(port
		(pt 160 72)
		(output)
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		(text "outclk_0" (rect 117 61 165 72)(font "Arial" (font_size 8)))
		(line (pt 160 72)(pt 112 72)(line_width 1))
	)
	(port
		(pt 160 112)
		(output)
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		(text "outclk_1" (rect 119 101 167 112)(font "Arial" (font_size 8)))
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	(port
		(pt 160 152)
		(output)
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	(drawing
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)