# WWW.FPGAArcade.COM # REPLAY 1.0 # Retro Gaming Platform # No Emulation No Compromise # # All rights reserved # Mike Johnson 2010 CONFIG PART = XC3S1600E-FG320-4 ; NET i_clk_a TNM_NET = clk_a_grp; NET i_clk_b TNM_NET = clk_b_grp; NET i_clk_c TNM_NET = clk_c_grp; #TIMESPEC TS03 = PERIOD : clk_a_grp : 7.9 ; #typ #TIMESPEC TS02 = PERIOD : clk_b_grp : 20.1 ; #typ #TIMESPEC TS01 = PERIOD : clk_c_grp : 36.9 ; #typ TIMESPEC TS03 = PERIOD : clk_a_grp : 7.5 ; #w.c. (-5%) TIMESPEC TS02 = PERIOD : clk_b_grp : 19.1 ; #w.c. (-5%) TIMESPEC TS01 = PERIOD : clk_c_grp : 35.0 ; #w.c. (-5%) TIMESPEC TS11=FROM:PADS:TO:FFS : 30 ns; TIMESPEC TS12=FROM:FFS:TO:PADS : 30 ns; INST "u_ClockGen/u_a_dcm" LOC = "DCM_X2Y0"; INST "u_ClockGen/phase_ctrl.u_a2_dcm" LOC = "DCM_X1Y0"; INST "u_ClockGen/u_b_dcm" LOC = "DCM_X2Y3"; INST "u_ClockGen/u_c_dcm" LOC = "DCM_X1Y3"; #clock phase delay not important, between the two A dcms it does matter - force local routing # better result than one direct and one not NET "i_clk_a" CLOCK_DEDICATED_ROUTE = FALSE; PIN "u_ClockGen/u_a_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; PIN "u_ClockGen/phase_ctrl.u_a2_dcm" CLOCK_DEDICATED_ROUTE = FALSE; NET "u_ClockGen/clk_a_ibuf" MAXSKEW = 0.3 ns; INST "u_ClockGen/u_dcm_a_clk_div_bufg" LOC = "BUFGMUX_X1Y1"; INST "u_ClockGen/u_dcm_a_clk_0_bufg" LOC = "BUFGMUX_X2Y1"; INST "u_ClockGen/u_dcm_a_clk_90_bufg" LOC = "BUFGMUX_X1Y0"; INST "u_ClockGen/phase_ctrl.u_dcm_a2_clk_bufg" LOC = "BUFGMUX_X2Y0"; # C is routed to reset generator, phase not important NET "i_clk_c" CLOCK_DEDICATED_ROUTE = FALSE; PIN "u_ClockGen/u_c_dcm.CLKIN" CLOCK_DEDICATED_ROUTE = FALSE; INST "u_ClockGen/u_dcm_c_clk_0_bufg" LOC = "BUFGMUX_X2Y10"; INST "u_ClockGen/u_dcm_c_clk_90_bufg" LOC = "BUFGMUX_X2Y11"; INST "u_spi_bufg" LOC = "BUFGMUX_X1Y11"; NET "i_fpga_spi_clk" TNM_NET = spi_clk; TIMESPEC TS_I_FPGA_SPI_CLK = PERIOD "spi_clk" 20 ns HIGH 50%; # domain crossing NET clk_ram TNM_NET = clk_ram_grp; NET clk_capture TNM_NET = clk_capture_grp; NET clk_ctl TNM_NET = clk_ctl_grp; # warning that it is ignored, so commented out #TIMESPEC TS_20 = FROM "clk_ctl_grp" TO "clk_capture_grp" TIG; TIMESPEC TS_21 = FROM "clk_ram_grp" TO "clk_capture_grp" TIG; TIMESPEC TS_22 = FROM "clk_capture_grp" TO "clk_ram_grp" TIG; # area constraints INST "u_Syscon/u_spi" AREA_GROUP = "AG_u_Syscon/u_spi" ; AREA_GROUP "AG_u_Syscon/u_spi" RANGE = SLICE_X32Y149:SLICE_X41Y140 ; INST "u_FileIO/u_spi" AREA_GROUP = "AG_u_FileIO/u_spi" ; AREA_GROUP "AG_u_FileIO/u_spi" RANGE = SLICE_X42Y149:SLICE_X49Y140 ; INST "u_DDRCtrl/u_ddr_ctrl/u_datapath" AREA_GROUP = "AG_u_DDRCtrl/u_ddr_ctrl/u_datapath" ; AREA_GROUP "AG_u_DDRCtrl/u_ddr_ctrl/u_datapath" RANGE = SLICE_X112Y0:SLICE_X115Y151 ; INST "u_ClockGen/u_reset" AREA_GROUP = "AG_u_ClockGen/u_reset" ; AREA_GROUP "AG_u_ClockGen/u_reset" RANGE = SLICE_X50Y143:SLICE_X55Y138 ; #INST "u_spi_input_mux" LOC = "SLICE_X47Y151"; # # 3V3 # NET "i_rs232_rxd" LOC = "A3" | IOSTANDARD = LVTTL; NET "b_aux_io(37)" LOC = "C3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_rs232_rts" LOC = "A4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(0)" LOC = "B4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(2)" LOC = "C4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_rs232_cts" LOC = "A5" | IOSTANDARD = LVTTL; NET "i_joy_a(5)" LOC = "B5" | IOSTANDARD = LVTTL | PULLUP; NET "o_rs232_txd" LOC = "C5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(5)" LOC = "D5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(26)" LOC = "A6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(38)" LOC = "B6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(6)" LOC = "D6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(7)" LOC = "E6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(29)" LOC = "A7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(9)" LOC = "C7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(10)" LOC = "D7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(12)" LOC = "E7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(3)" LOC = "F7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(27)" LOC = "A8" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_joy_b(0)" LOC = "B8" | IOSTANDARD = LVTTL | PULLUP; NET "i_joy_a(4)" LOC = "C8" | IOSTANDARD = LVTTL | PULLUP; NET "i_joy_a(1)" LOC = "D8" | IOSTANDARD = LVTTL | PULLUP; NET "b_fpga_spi_mosi" LOC = "E8" | IOSTANDARD = LVTTL; NET "b_aux_io(20)" LOC = "F8" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_joy_a(2)" LOC = "B9" | IOSTANDARD = LVTTL | PULLUP; NET "i_fpga_spi_clk" LOC = "C9" | IOSTANDARD = LVTTL; NET "b_aux_io(14)" LOC = "D9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(25)" LOC = "E9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_fpga_spi_miso" LOC = "F9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(15)" LOC = "G9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(32)" LOC = "A10" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_clk_b" LOC = "B10" | IOSTANDARD = LVTTL; NET "i_clk_c" LOC = "D10" | IOSTANDARD = LVTTL; NET "b_aux_io(17)" LOC = "E10" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_joy_b(3)" LOC = "F10" | IOSTANDARD = LVTTL | PULLUP; NET "i_joy_b(5)" LOC = "G10" | IOSTANDARD = LVTTL | PULLUP; NET "b_aux_io(8)" LOC = "A11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(21)" LOC = "B11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(23)" LOC = "C11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(22)" LOC = "D11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(34)" LOC = "E11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(36)" LOC = "F11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(24)" LOC = "A12" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_joy_a(0)" LOC = "C12" | IOSTANDARD = LVTTL | PULLUP; NET "i_joy_b(2)" LOC = "D12" | IOSTANDARD = LVTTL | PULLUP; NET "b_aux_io(35)" LOC = "E12" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(30)" LOC = "F12" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(13)" LOC = "A13" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(28)" LOC = "B13" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(31)" LOC = "D13" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_ps2a_data" LOC = "E13" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(11)" LOC = "A14" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(16)" LOC = "B14" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(33)" LOC = "C14" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_ps2a_clk" LOC = "D14" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_joy_a(3)" LOC = "A15" | IOSTANDARD = LVTTL | PULLUP; NET "i_joy_b(1)" LOC = "B15" | IOSTANDARD = LVTTL | PULLUP; NET "i_joy_b(4)" LOC = "C15" | IOSTANDARD = LVTTL | PULLUP; NET "b_aux_io(18)" LOC = "A16" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(19)" LOC = "B16" | IOSTANDARD = LVTTL | DRIVE = 8; # # 2V5 # #NET "" LOC = "B18"; # NC INP NET "o_mem_addr(2)" LOC = "C18" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(3)" LOC = "C17" | IOSTANDARD = SSTL2_I; #NET "" LOC = "D18"; # VREF NET "o_disk_led" LOC = "D17" | IOSTANDARD = LVCMOS25; NET "o_pwr_led" LOC = "D16" | IOSTANDARD = LVCMOS25; #NET "" LOC = "E18"; # NC INP #NET "" LOC = "E17"; # NC INP NET "b_2v5_io_1" LOC = "E16" | IOSTANDARD = LVCMOS25; NET "b_2v5_io_0" LOC = "E15" | IOSTANDARD = LVCMOS25; NET "o_mem_addr(1)" LOC = "F18" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(4)" LOC = "F17" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(0)" LOC = "F15" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(5)" LOC = "F14" | IOSTANDARD = SSTL2_I; #NET "" LOC = "G18"; # NC INP NET "o_mem_addr(10)" LOC = "G16" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(6)" LOC = "G15" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(14)" LOC = "G14" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(7)" LOC = "G13" | IOSTANDARD = SSTL2_I; #NET "" LOC = "H18"; # VREF NET "o_mem_addr(13)" LOC = "H17" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(8)" LOC = "H16" | IOSTANDARD = SSTL2_I; NET "o_mem_addr(9)" LOC = "H15" | IOSTANDARD = SSTL2_I; NET "o_mem_cs" LOC = "H14" | IOSTANDARD = SSTL2_I; # ctrl4 #NET "" LOC = "H13"; # NC INP NET "o_mem_addr(11)" LOC = "J17" | IOSTANDARD = SSTL2_I; NET "o_mem_ras" LOC = "J16" | IOSTANDARD = SSTL2_I; # ctrl3 NET "o_mem_addr(12)" LOC = "J15" | IOSTANDARD = SSTL2_I; NET "o_mem_cas" LOC = "J14" | IOSTANDARD = SSTL2_I; # ctrl2 NET "o_mem_cke" LOC = "J13" | IOSTANDARD = SSTL2_I; # ctrl0 NET "o_mem_we" LOC = "J12" | IOSTANDARD = SSTL2_I; # ctrl1 #NET "" LOC = "K18"; # NC INP #NET "" LOC = "K17"; # NC INP NET "o_mem_clk_p" LOC = "K15" | IOSTANDARD = SSTL2_I; NET "o_mem_clk_n" LOC = "K14" | IOSTANDARD = SSTL2_I; NET "o_mem_udm" LOC = "K13" | IOSTANDARD = SSTL2_I; # ctrl6 NET "o_mem_ldm" LOC = "K12" | IOSTANDARD = SSTL2_I; # ctrl5 NET "b_mem_udqs" LOC = "L18" | IOSTANDARD = SSTL2_I; # ctrl8 #NET "" LOC = "L17"; # VREF NET "b_mem_dq(8)" LOC = "L16" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(10)" LOC = "L15" | IOSTANDARD = SSTL2_I; #NET "" LOC = "L14"; # NC INP #NET "" LOC = "L13"; # NC INP NET "b_mem_dq(7)" LOC = "M18" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(9)" LOC = "M16" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(6)" LOC = "M15" | IOSTANDARD = SSTL2_I; NET "b_mem_ldqs" LOC = "M14" | IOSTANDARD = SSTL2_I; # ctrl7 #NET "" LOC = "M13" # VREF NET "b_mem_dq(5)" LOC = "N18" | IOSTANDARD = SSTL2_I; #NET "" LOC = "N17"; # NC INP NET "b_mem_dq(4)" LOC = "N15" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(11)" LOC = "N14" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(3)" LOC = "P18" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(12)" LOC = "P17" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(13)" LOC = "P16" | IOSTANDARD = SSTL2_I; NET "i_ext_rst_l" LOC = "P15" | IOSTANDARD = LVCMOS25 | PULLUP; NET "b_mem_dq(2)" LOC = "R18" | IOSTANDARD = SSTL2_I; #NET "" LOC = "R17"; # NC INP #NET "" LOC = "R16"; # VREF NET "b_mem_dq(14)" LOC = "R15" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(1)" LOC = "T18" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(0)" LOC = "T17" | IOSTANDARD = SSTL2_I; NET "b_mem_dq(15)" LOC = "U18" | IOSTANDARD = SSTL2_I; # # 3V3 # NET "i_video_int" LOC = "V16" | IOSTANDARD = LVTTL; #video15 NET "o_audio_lrcin" LOC = "T16" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_audio_mclk" LOC = "V15" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_audio_bckin" LOC = "U15" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_audio_din" LOC = "T15" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_fpga_ctrl1" LOC = "V14" | IOSTANDARD = LVTTL; NET "i_fpga_ctrl0" LOC = "U14" | IOSTANDARD = LVTTL; NET "b_ps2b_data" LOC = "T14" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_ps2b_clk" LOC = "R14" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(7)" LOC = "V13" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(0)" LOC = "U13" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_rst_l" LOC = "R13" | IOSTANDARD = LVTTL | DRIVE = 8; # video16 NET "o_video_de" LOC = "P13" | IOSTANDARD = LVTTL | DRIVE = 8; # video14 NET "o_video_data(2)" LOC = "V12" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(1)" LOC = "T12" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_v" LOC = "R12" | IOSTANDARD = LVTTL | DRIVE = 8; #video13 NET "o_video_h" LOC = "P12" | IOSTANDARD = LVTTL | DRIVE = 8; #video12 NET "o_video_data(4)" LOC = "N12" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(0)" LOC = "U11" | IOSTANDARD = LVTTL | PULLUP; NET "i_aux_ip(6)" LOC = "T11" | IOSTANDARD = LVTTL | PULLUP; NET "o_video_data(5)" LOC = "R11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(3)" LOC = "P11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(8)" LOC = "N11" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_clk_a" LOC = "U10" | IOSTANDARD = LVTTL; NET "b_scl" LOC = "R10" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_sda" LOC = "P10" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_clk_n" LOC = "V9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_clk_p" LOC = "U9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(9)" LOC = "R9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(6)" LOC = "P9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_clk_aux" LOC = "N9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_clk_68k" LOC = "M9" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(2)" LOC = "V8" | IOSTANDARD = LVTTL | PULLUP; NET "i_aux_ip(1)" LOC = "U8" | IOSTANDARD = LVTTL | PULLUP; NET "o_video_data(10)" LOC = "T8" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_data(11)" LOC = "R8" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_hsync" LOC = "P8" | IOSTANDARD = LVTTL | DRIVE = 8; NET "o_video_vsync" LOC = "N8" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_video_ddc_clk" LOC = "V7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(4)" LOC = "T7" | IOSTANDARD = LVTTL | PULLUP; NET "i_aux_ip(3)" LOC = "R7" | IOSTANDARD = LVTTL | PULLUP; NET "b_video_ddc_data" LOC = "P7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(15)" LOC = "N7" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_video_spc" LOC = "V6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(0)" LOC = "U6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(1)" LOC = "R6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(2)" LOC = "P6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(3)" LOC = "V5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(4)" LOC = "U5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(5)" LOC = "T5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(6)" LOC = "R5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(5)" LOC = "V4" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(7)" LOC = "T4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(7)" LOC = "V3" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(8)" LOC = "U3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(8)" LOC = "V2" | IOSTANDARD = LVTTL | PULLUP; # # 3V3 # NET "i_aux_ip(9)" LOC = "U1" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(9)" LOC = "T1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(10)" LOC = "T2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(10)" LOC = "R1" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(11)" LOC = "R2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(12)" LOC = "R3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(11)" LOC = "R4" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(13)" LOC = "P1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(14)" LOC = "P2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_video_spd" LOC = "P3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(43)" LOC = "P4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(12)" LOC = "N1" | IOSTANDARD = LVTTL | PULLUP; NET "i_aux_ip(13)" LOC = "N2" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(42)" LOC = "N4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(41)" LOC = "N5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(14)" LOC = "M1" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(40)" LOC = "M3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(27)" LOC = "M4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(26)" LOC = "M5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(25)" LOC = "M6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(24)" LOC = "L1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(23)" LOC = "L2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(22)" LOC = "L3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(21)" LOC = "L4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(20)" LOC = "L5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(19)" LOC = "L6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(15)" LOC = "K2" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(18)" LOC = "K3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(17)" LOC = "K4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(16)" LOC = "K5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(44)" LOC = "K6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(16)" LOC = "K7" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(45)" LOC = "J1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(46)" LOC = "J2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(47)" LOC = "J4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(48)" LOC = "J5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(17)" LOC = "J6" | IOSTANDARD = LVTTL | PULLUP; NET "i_aux_ip(18)" LOC = "J7" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(49)" LOC = "H1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(50)" LOC = "H2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(51)" LOC = "H3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(52)" LOC = "H4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(53)" LOC = "H5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(54)" LOC = "H6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(19)" LOC = "G1" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(39)" LOC = "G3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(38)" LOC = "G4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(37)" LOC = "G5" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(36)" LOC = "G6" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(35)" LOC = "F1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(34)" LOC = "F2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(20)" LOC = "F4" | IOSTANDARD = LVTTL | PULLUP; NET "i_aux_ip(21)" LOC = "F5" | IOSTANDARD = LVTTL | PULLUP; NET "b_io(33)" LOC = "E1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(32)" LOC = "E2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(31)" LOC = "E3" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(30)" LOC = "E4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(29)" LOC = "D1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_io(28)" LOC = "D2" | IOSTANDARD = LVTTL | DRIVE = 8; NET "i_aux_ip(22)" LOC = "D3" | IOSTANDARD = LVTTL | PULLUP; NET "b_aux_io(1)" LOC = "D4" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(39)" LOC = "C1" | IOSTANDARD = LVTTL | DRIVE = 8; NET "b_aux_io(4)" LOC = "C2" | IOSTANDARD = LVTTL | DRIVE = 8; #NET "i_ssc_tf" LOC = "T3" | IOSTANDARD = LVTTL; #NET "i_ssc_td" LOC = "N10" | IOSTANDARD = LVTTL; #NET "i_ssc_rk" LOC = "U16" | IOSTANDARD = LVTTL; NET "o_ssc_rd" LOC = "U4" | IOSTANDARD = LVTTL | DRIVE = 8;