Welcome to Xilinx CORE Generator. Help system initialized. The IP Catalog has been reloaded. Wrote CGP file for project 'coregen'. Customize and GenerateINFO:sim:172 - Generating IP... Applying current project options... Finished applying current project options. Resolving generics for 'pll_5'... Applying external generics to 'pll_5'... Delivering associated files for 'pll_5'... WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for VHDL synthesis Delivering EJava files for 'pll_5'... Delivered 3 files into directory /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_5 Delivered 1 file into directory /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_5 Generating ASY schematic symbol... Loading device for application Rf_Device from file '6slx9.nph' in environment /home/markw/fpga/xilinx/14.7/ISE_DS/ISE/. INFO:sim:949 - Finished generation of ASY schematic symbol. Generating ISE project... XCO file found: pll_5.xco XMDF file found: pll_5_xmdf.tcl Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_5.asy -view all -origin_type imported Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_5.ucf -view all -origin_type created Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_5.vhd -view all -origin_type created INFO:HDLCompiler:1061 - Parsing VHDL file "/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_ cg/pll_5.vhd" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_5.vho -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. Top level has been set to "/pll_5" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Launching README viewer... Moving files to output directory... Finished moving files to output directory Saved CGP file for project 'coregen'. Customize and GenerateINFO:sim:172 - Generating IP... Applying current project options... Finished applying current project options. Resolving generics for 'pll_pal'... Applying external generics to 'pll_pal'... Delivering associated files for 'pll_pal'... WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for VHDL synthesis Delivering EJava files for 'pll_pal'... Delivered 3 files into directory /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_pal Delivered 1 file into directory /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_pal Generating ASY schematic symbol... INFO:sim:949 - Finished generation of ASY schematic symbol. Generating ISE project... XCO file found: pll_pal.xco XMDF file found: pll_pal_xmdf.tcl Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_pal.asy -view all -origin_type imported Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_pal.ucf -view all -origin_type created Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_pal.vhd -view all -origin_type created INFO:HDLCompiler:1061 - Parsing VHDL file "/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_ cg/pll_pal.vhd" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_pal.vho -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. Top level has been set to "/pll_pal" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Launching README viewer... Moving files to output directory... Finished moving files to output directory Saved CGP file for project 'coregen'. Customize and GenerateINFO:sim:172 - Generating IP... Applying current project options... Finished applying current project options. Resolving generics for 'pll_ntsc'... Applying external generics to 'pll_ntsc'... Delivering associated files for 'pll_ntsc'... WARNING:sim - Component clk_wiz_v3_6 does not have a valid model name for VHDL synthesis Delivering EJava files for 'pll_ntsc'... Delivered 3 files into directory /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_ntsc Delivered 1 file into directory /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_ntsc Generating ASY schematic symbol... INFO:sim:949 - Finished generation of ASY schematic symbol. Generating ISE project... XCO file found: pll_ntsc.xco XMDF file found: pll_ntsc_xmdf.tcl Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_ntsc.asy -view all -origin_type imported Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_ntsc.ucf -view all -origin_type created Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_ntsc.vhd -view all -origin_type created INFO:HDLCompiler:1061 - Parsing VHDL file "/home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_ cg/pll_ntsc.vhd" into library work INFO:ProjectMgmt - Parsing design hierarchy completed successfully. Adding /home/markw/fpga/svn/repo/trunk/atari_800xl/papilioduo/plls/ipcore_dir/tmp/_cg/p ll_ntsc.vho -view all -origin_type imported INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off. Please set the new top explicitly by running the "project set top" command. To re-calculate the new top automatically, set the "Auto Implementation Top" property to true. Top level has been set to "/pll_ntsc" Generating README file... Generating FLIST file... INFO:sim:948 - Finished FLIST file generation. Launching README viewer... Moving files to output directory... Finished moving files to output directory Saved CGP file for project 'coregen'. Closed project file.