xilinx.com CoreGen coregen 1.0 pll_5 pll_5 true true false false false No_Jitter false false 32 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 312.5 100.0 false false false false false false 1 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 5 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin64 empty true DONE false false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 32 5 false 31.250 NONE SYSTEM_SYNCHRONOUS 0 1X false CLKFX CLKFX CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 23 0.000 CLKFBOUT 1 31.250 SYSTEM_SYNCHRONOUS 0.010 13 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 0 0 0 0 0 0 pll_5 lin64 1 1 0.010 0.010 No_Jitter 0 0 0 0 0 0 0 0 DCM_SP 0 32 Units_MHz 100.000 FDBK_AUTO Single_ended_clock_capable_pin Single_ended_clock_capable_pin SINGLE 0 1 0 0 0 0 0 1 BUFG BUFG BUFG BUFG BUFG BUFG BUFG __primary______________32____________0.010 no_secondary_input_clock CLK_OUT1_____5.000______0.000______50.0_____4200.000____150.000 no_CLK_OUT2_output no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 5 100.000 100.000 100.000 100.000 100.000 100.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 5.000 N/A N/A N/A N/A N/A N/A 0.000 N/A N/A N/A N/A N/A N/A 50.0 N/A N/A N/A N/A N/A N/A None OPTIMIZED 4.000 10.000 10.000 FALSE FALSE ZHOLD 1 0.010 0.010 FALSE 4.000 1 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE None OPTIMIZED CLKFBOUT 23 31.250 SYSTEM_SYNCHRONOUS 1 0.010 13 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 None 2.000 32 5 FALSE 31.25 NONE 1X BUFG SYSTEM_SYNCHRONOUS 0 FALSE CLKFX NONE NONE NONE NONE NONE None 2 1 4 31.25 0.000 NONE FALSE CLKFX NONE NONE AUTO 0 0 0 0 NONE CLK_IN1 CLK_IN2 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 RESET LOCKED CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N POWER_DOWN DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED 312.5 100.0 MMCM CENTER_HIGH 4000 coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -3 BusFormatAngleBracketNotRipped VHDL true Other false false false Ngc false Behavioral VHDL false 2012-05-10+12:44 apply_current_project_options_generator customization_generator model_parameter_resolution_generator ip_xco_generator ./pll_5.xco xco Wed Mar 18 20:09:55 GMT 2015 0x7A7E9F98 generationID_1879581046 tcl_flow_generator ./pll_5/example_design/pll_5_exdes.ucf ignore ucf Wed Mar 18 20:10:00 GMT 2015 0x0725DDE3 generationID_1879581046 ./pll_5/example_design/pll_5_exdes.vhd ignore vhdl Wed Mar 18 20:09:56 GMT 2015 0xDF1A9D05 generationID_1879581046 ./pll_5/example_design/pll_5_exdes.xdc ignore xdc Wed Mar 18 20:10:00 GMT 2015 0x28890D30 generationID_1879581046 ./pll_5/implement/implement.bat ignore unknown Wed Mar 18 20:10:00 GMT 2015 0x679DC9DC generationID_1879581046 ./pll_5/implement/implement.sh ignore unknown Wed Mar 18 20:10:00 GMT 2015 0xAF2D127F generationID_1879581046 ./pll_5/implement/planAhead_ise.bat ignore unknown Wed Mar 18 20:09:59 GMT 2015 0x6966A508 generationID_1879581046 ./pll_5/implement/planAhead_ise.sh ignore unknown Wed Mar 18 20:09:59 GMT 2015 0x7F8B5943 generationID_1879581046 ./pll_5/implement/planAhead_ise.tcl ignore tcl Wed Mar 18 20:09:59 GMT 2015 0x204C67A6 generationID_1879581046 ./pll_5/implement/planAhead_rdn.bat ignore unknown Wed Mar 18 20:09:59 GMT 2015 0xB9373CFA generationID_1879581046 ./pll_5/implement/planAhead_rdn.sh ignore unknown Wed Mar 18 20:09:59 GMT 2015 0xDCE9D96C generationID_1879581046 ./pll_5/implement/planAhead_rdn.tcl ignore tcl Wed Mar 18 20:10:00 GMT 2015 0x9C3471F7 generationID_1879581046 ./pll_5/implement/xst.prj ignore unknown Wed Mar 18 20:10:00 GMT 2015 0xD85E032D generationID_1879581046 ./pll_5/implement/xst.scr ignore unknown Wed Mar 18 20:10:00 GMT 2015 0x4A661936 generationID_1879581046 ./pll_5/simulation/functional/simcmds.tcl ignore tcl Wed Mar 18 20:09:58 GMT 2015 0x4DA4A9C8 generationID_1879581046 ./pll_5/simulation/functional/simulate_isim.bat ignore unknown Wed Mar 18 20:09:58 GMT 2015 0x3B21C8E1 generationID_1879581046 ./pll_5/simulation/functional/simulate_isim.sh ignore unknown Wed Mar 18 20:09:58 GMT 2015 0x6B3CA9A8 generationID_1879581046 ./pll_5/simulation/functional/simulate_mti.bat ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x858EA406 generationID_1879581046 ./pll_5/simulation/functional/simulate_mti.do ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x11139D32 generationID_1879581046 ./pll_5/simulation/functional/simulate_mti.sh ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x668BD918 generationID_1879581046 ./pll_5/simulation/functional/simulate_ncsim.sh ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x3C531A19 generationID_1879581046 ./pll_5/simulation/functional/simulate_vcs.sh ignore unknown Wed Mar 18 20:09:58 GMT 2015 0x75EF921A generationID_1879581046 ./pll_5/simulation/functional/wave.do ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x3C373DFA generationID_1879581046 ./pll_5/simulation/functional/wave.sv ignore unknown Wed Mar 18 20:09:58 GMT 2015 0x7B3A6DA0 generationID_1879581046 ./pll_5/simulation/pll_5_tb.vhd ignore vhdl Wed Mar 18 20:09:56 GMT 2015 0x905A12D4 generationID_1879581046 ./pll_5/simulation/timing/pll_5_tb.vhd ignore vhdl Wed Mar 18 20:09:56 GMT 2015 0xAFA210EF generationID_1879581046 ./pll_5/simulation/timing/sdf_cmd_file ignore unknown Wed Mar 18 20:09:58 GMT 2015 0xA481C77B generationID_1879581046 ./pll_5/simulation/timing/simcmds.tcl ignore tcl Wed Mar 18 20:09:58 GMT 2015 0x0339FBD3 generationID_1879581046 ./pll_5/simulation/timing/simulate_isim.sh ignore unknown Wed Mar 18 20:09:58 GMT 2015 0x7B494E8B generationID_1879581046 ./pll_5/simulation/timing/simulate_mti.bat ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x926A1FC3 generationID_1879581046 ./pll_5/simulation/timing/simulate_mti.do ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x55D51444 generationID_1879581046 ./pll_5/simulation/timing/simulate_mti.sh ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x0B3F4688 generationID_1879581046 ./pll_5/simulation/timing/simulate_ncsim.sh ignore unknown Wed Mar 18 20:09:57 GMT 2015 0xF7261913 generationID_1879581046 ./pll_5/simulation/timing/simulate_vcs.sh ignore unknown Wed Mar 18 20:09:59 GMT 2015 0x479C6559 generationID_1879581046 ./pll_5/simulation/timing/ucli_commands.key ignore unknown Wed Mar 18 20:09:59 GMT 2015 0x37782F99 generationID_1879581046 ./pll_5/simulation/timing/vcs_session.tcl ignore tcl Wed Mar 18 20:09:59 GMT 2015 0x28340249 generationID_1879581046 ./pll_5/simulation/timing/wave.do ignore unknown Wed Mar 18 20:09:57 GMT 2015 0x1661427B generationID_1879581046 ./pll_5.ucf ucf Wed Mar 18 20:10:00 GMT 2015 0x750EB57B generationID_1879581046 ./pll_5.vhd vhdl Wed Mar 18 20:09:55 GMT 2015 0xF23B3EFD generationID_1879581046 ./pll_5.vho vho Wed Mar 18 20:09:56 GMT 2015 0xF14778B3 generationID_1879581046 ./pll_5.xdc ignore xdc Wed Mar 18 20:10:00 GMT 2015 0x4C651AF1 generationID_1879581046 ./pll_5_xmdf.tcl tcl Wed Mar 18 20:09:56 GMT 2015 0xA66ADA17 generationID_1879581046 associated_files_generator ./pll_5/clk_wiz_v3_6_readme.txt ignore txt Sun Oct 13 18:34:18 GMT 2013 0x5B63DA78 generationID_1879581046 ejava_generator ./pll_5/example_design/pll_5_exdes.ucf ignore ucf Wed Mar 18 20:10:01 GMT 2015 0x0725DDE3 generationID_1879581046 ./pll_5/example_design/pll_5_exdes.vhd ignore vhdl Wed Mar 18 20:10:01 GMT 2015 0xDF1A9D05 generationID_1879581046 ./pll_5/example_design/pll_5_exdes.xdc ignore xdc Wed Mar 18 20:10:01 GMT 2015 0x28890D30 generationID_1879581046 ./pll_5/implement/implement.bat ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x679DC9DC generationID_1879581046 ./pll_5/implement/implement.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0xAF2D127F generationID_1879581046 ./pll_5/implement/planAhead_ise.bat ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x6966A508 generationID_1879581046 ./pll_5/implement/planAhead_ise.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x7F8B5943 generationID_1879581046 ./pll_5/implement/planAhead_ise.tcl ignore tcl Wed Mar 18 20:10:01 GMT 2015 0x204C67A6 generationID_1879581046 ./pll_5/implement/planAhead_rdn.bat ignore unknown Wed Mar 18 20:10:01 GMT 2015 0xB9373CFA generationID_1879581046 ./pll_5/implement/planAhead_rdn.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0xDCE9D96C generationID_1879581046 ./pll_5/implement/planAhead_rdn.tcl ignore tcl Wed Mar 18 20:10:01 GMT 2015 0x9C3471F7 generationID_1879581046 ./pll_5/implement/xst.prj ignore unknown Wed Mar 18 20:10:01 GMT 2015 0xD85E032D generationID_1879581046 ./pll_5/implement/xst.scr ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x4A661936 generationID_1879581046 ./pll_5/simulation/functional/simcmds.tcl ignore tcl Wed Mar 18 20:10:01 GMT 2015 0x4DA4A9C8 generationID_1879581046 ./pll_5/simulation/functional/simulate_isim.bat ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x3B21C8E1 generationID_1879581046 ./pll_5/simulation/functional/simulate_isim.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x6B3CA9A8 generationID_1879581046 ./pll_5/simulation/functional/simulate_mti.bat ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x858EA406 generationID_1879581046 ./pll_5/simulation/functional/simulate_mti.do ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x11139D32 generationID_1879581046 ./pll_5/simulation/functional/simulate_mti.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x668BD918 generationID_1879581046 ./pll_5/simulation/functional/simulate_ncsim.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x3C531A19 generationID_1879581046 ./pll_5/simulation/functional/simulate_vcs.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x75EF921A generationID_1879581046 ./pll_5/simulation/functional/wave.do ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x3C373DFA generationID_1879581046 ./pll_5/simulation/functional/wave.sv ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x7B3A6DA0 generationID_1879581046 ./pll_5/simulation/pll_5_tb.vhd ignore vhdl Wed Mar 18 20:10:01 GMT 2015 0x905A12D4 generationID_1879581046 ./pll_5/simulation/timing/pll_5_tb.vhd ignore vhdl Wed Mar 18 20:10:01 GMT 2015 0xAFA210EF generationID_1879581046 ./pll_5/simulation/timing/sdf_cmd_file ignore unknown Wed Mar 18 20:10:01 GMT 2015 0xA481C77B generationID_1879581046 ./pll_5/simulation/timing/simcmds.tcl ignore tcl Wed Mar 18 20:10:01 GMT 2015 0x0339FBD3 generationID_1879581046 ./pll_5/simulation/timing/simulate_isim.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x7B494E8B generationID_1879581046 ./pll_5/simulation/timing/simulate_mti.bat ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x926A1FC3 generationID_1879581046 ./pll_5/simulation/timing/simulate_mti.do ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x55D51444 generationID_1879581046 ./pll_5/simulation/timing/simulate_mti.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x0B3F4688 generationID_1879581046 ./pll_5/simulation/timing/simulate_ncsim.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0xF7261913 generationID_1879581046 ./pll_5/simulation/timing/simulate_vcs.sh ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x479C6559 generationID_1879581046 ./pll_5/simulation/timing/ucli_commands.key ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x37782F99 generationID_1879581046 ./pll_5/simulation/timing/vcs_session.tcl ignore tcl Wed Mar 18 20:10:01 GMT 2015 0x28340249 generationID_1879581046 ./pll_5/simulation/timing/wave.do ignore unknown Wed Mar 18 20:10:01 GMT 2015 0x1661427B generationID_1879581046 ./pll_5.ucf ucf Wed Mar 18 20:10:01 GMT 2015 0x750EB57B generationID_1879581046 ./pll_5.vhd vhdl Wed Mar 18 20:10:01 GMT 2015 0xF23B3EFD generationID_1879581046 ./pll_5.vho vho Wed Mar 18 20:10:01 GMT 2015 0xF14778B3 generationID_1879581046 ./pll_5.xdc ignore xdc Wed Mar 18 20:10:01 GMT 2015 0x4C651AF1 generationID_1879581046 ./pll_5_xmdf.tcl tcl Wed Mar 18 20:10:01 GMT 2015 0xA66ADA17 generationID_1879581046 all_documents_generator ./pll_5/doc/clk_wiz_v3_6_readme.txt ignore txt Wed Mar 18 20:10:06 GMT 2015 0x5B63DA78 generationID_1879581046 ./pll_5/doc/clk_wiz_v3_6_vinfo.html ignore unknown Wed Mar 18 20:10:06 GMT 2015 0xF2E77607 generationID_1879581046 ./pll_5/doc/pg065_clk_wiz.pdf ignore pdf Wed Mar 18 20:10:06 GMT 2015 0xCE1EE896 generationID_1879581046 readme_documents_generator asy_generator ./pll_5.asy asy Wed Mar 18 20:10:11 GMT 2015 0x0F990A02 generationID_1879581046 ise_generator ./pll_5.gise ignore gise Wed Mar 18 20:10:14 GMT 2015 0x3EEE9BF6 generationID_1879581046 ./pll_5.xise ignore xise Wed Mar 18 20:10:14 GMT 2015 0x4C43C3B3 generationID_1879581046 deliver_readme_generator flist_generator ./pll_5_flist.txt ignore txtFlist txt Wed Mar 18 20:10:14 GMT 2015 0x071A4544 generationID_1879581046 view_readme_generator pll_pal pll_pal true true false false false No_Jitter false false 32 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 312.5 100.0 false false false false false false 1 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 56.75 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin64 empty true DONE true false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 1 4 false 100.000 NONE SYSTEM_SYNCHRONOUS 0 1X false CLK0 CLK0 CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 23 0.000 CLKFBOUT 1 31.250 SYSTEM_SYNCHRONOUS 0.010 13 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 0 0 0 0 0 0 pll_pal lin64 1 1 0.010 0.010 No_Jitter 0 0 0 0 0 0 0 0 PLL_BASE 0 32 Units_MHz 100.000 FDBK_AUTO Single_ended_clock_capable_pin Single_ended_clock_capable_pin SINGLE 1 1 0 0 0 0 0 1 BUFG BUFG BUFG BUFG BUFG BUFG BUFG __primary______________32____________0.010 no_secondary_input_clock CLK_OUT1____56.615______0.000______50.0______305.664____206.192 no_CLK_OUT2_output no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 56.75 100.000 100.000 100.000 100.000 100.000 100.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 56.615 N/A N/A N/A N/A N/A N/A 0.000 N/A N/A N/A N/A N/A N/A 50.0 N/A N/A N/A N/A N/A N/A None OPTIMIZED 4.000 10.000 10.000 FALSE FALSE ZHOLD 1 0.010 0.010 FALSE 4.000 1 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE None OPTIMIZED CLKFBOUT 23 31.250 SYSTEM_SYNCHRONOUS 1 0.010 13 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 None 2.000 1 4 FALSE 31.25 NONE 1X BUFG SYSTEM_SYNCHRONOUS 0 FALSE CLK0 NONE NONE NONE NONE NONE None 2 1 4 31.25 0.000 NONE FALSE CLKFX NONE NONE AUTO 0 0 0 0 NONE CLK_IN1 CLK_IN2 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 RESET LOCKED CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N POWER_DOWN DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED 312.5 100.0 MMCM CENTER_HIGH 4000 coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -3 BusFormatAngleBracketNotRipped VHDL true Other false false false Ngc false Behavioral VHDL false 2012-05-10+12:44 apply_current_project_options_generator customization_generator model_parameter_resolution_generator ip_xco_generator ./pll_pal.xco xco Wed Mar 18 20:14:27 GMT 2015 0x3CD9F5CF generationID_706127423 tcl_flow_generator ./pll_pal/example_design/pll_pal_exdes.ucf ignore ucf Wed Mar 18 20:14:32 GMT 2015 0x96B868C6 generationID_706127423 ./pll_pal/example_design/pll_pal_exdes.vhd ignore vhdl Wed Mar 18 20:14:28 GMT 2015 0xAC34E26B generationID_706127423 ./pll_pal/example_design/pll_pal_exdes.xdc ignore xdc Wed Mar 18 20:14:32 GMT 2015 0xC6047BF4 generationID_706127423 ./pll_pal/implement/implement.bat ignore unknown Wed Mar 18 20:14:32 GMT 2015 0xC84918A2 generationID_706127423 ./pll_pal/implement/implement.sh ignore unknown Wed Mar 18 20:14:32 GMT 2015 0x29768185 generationID_706127423 ./pll_pal/implement/planAhead_ise.bat ignore unknown Wed Mar 18 20:14:31 GMT 2015 0x6966A508 generationID_706127423 ./pll_pal/implement/planAhead_ise.sh ignore unknown Wed Mar 18 20:14:31 GMT 2015 0x7F8B5943 generationID_706127423 ./pll_pal/implement/planAhead_ise.tcl ignore tcl Wed Mar 18 20:14:32 GMT 2015 0xA63124E3 generationID_706127423 ./pll_pal/implement/planAhead_rdn.bat ignore unknown Wed Mar 18 20:14:32 GMT 2015 0xB9373CFA generationID_706127423 ./pll_pal/implement/planAhead_rdn.sh ignore unknown Wed Mar 18 20:14:32 GMT 2015 0xDCE9D96C generationID_706127423 ./pll_pal/implement/planAhead_rdn.tcl ignore tcl Wed Mar 18 20:14:32 GMT 2015 0xE19DDED9 generationID_706127423 ./pll_pal/implement/xst.prj ignore unknown Wed Mar 18 20:14:33 GMT 2015 0x5236CC8F generationID_706127423 ./pll_pal/implement/xst.scr ignore unknown Wed Mar 18 20:14:33 GMT 2015 0xAE14CC56 generationID_706127423 ./pll_pal/simulation/functional/simcmds.tcl ignore tcl Wed Mar 18 20:14:30 GMT 2015 0xA87F2772 generationID_706127423 ./pll_pal/simulation/functional/simulate_isim.bat ignore unknown Wed Mar 18 20:14:30 GMT 2015 0xD64D1B14 generationID_706127423 ./pll_pal/simulation/functional/simulate_isim.sh ignore unknown Wed Mar 18 20:14:30 GMT 2015 0x817C1754 generationID_706127423 ./pll_pal/simulation/functional/simulate_mti.bat ignore unknown Wed Mar 18 20:14:29 GMT 2015 0x5620C7DE generationID_706127423 ./pll_pal/simulation/functional/simulate_mti.do ignore unknown Wed Mar 18 20:14:29 GMT 2015 0xD2996AE5 generationID_706127423 ./pll_pal/simulation/functional/simulate_mti.sh ignore unknown Wed Mar 18 20:14:29 GMT 2015 0x08E1E243 generationID_706127423 ./pll_pal/simulation/functional/simulate_ncsim.sh ignore unknown Wed Mar 18 20:14:30 GMT 2015 0x10C555F7 generationID_706127423 ./pll_pal/simulation/functional/simulate_vcs.sh ignore unknown Wed Mar 18 20:14:31 GMT 2015 0x96FB469F generationID_706127423 ./pll_pal/simulation/functional/wave.do ignore unknown Wed Mar 18 20:14:29 GMT 2015 0x9669CD8D generationID_706127423 ./pll_pal/simulation/functional/wave.sv ignore unknown Wed Mar 18 20:14:30 GMT 2015 0x5DA2BE69 generationID_706127423 ./pll_pal/simulation/pll_pal_tb.vhd ignore vhdl Wed Mar 18 20:14:28 GMT 2015 0x62FDED61 generationID_706127423 ./pll_pal/simulation/timing/pll_pal_tb.vhd ignore vhdl Wed Mar 18 20:14:28 GMT 2015 0x1685662D generationID_706127423 ./pll_pal/simulation/timing/sdf_cmd_file ignore unknown Wed Mar 18 20:14:30 GMT 2015 0xA481C77B generationID_706127423 ./pll_pal/simulation/timing/simcmds.tcl ignore tcl Wed Mar 18 20:14:31 GMT 2015 0x28687ACF generationID_706127423 ./pll_pal/simulation/timing/simulate_isim.sh ignore unknown Wed Mar 18 20:14:30 GMT 2015 0xE7BCE5B1 generationID_706127423 ./pll_pal/simulation/timing/simulate_mti.bat ignore unknown Wed Mar 18 20:14:29 GMT 2015 0x98B4D657 generationID_706127423 ./pll_pal/simulation/timing/simulate_mti.do ignore unknown Wed Mar 18 20:14:29 GMT 2015 0x3569F171 generationID_706127423 ./pll_pal/simulation/timing/simulate_mti.sh ignore unknown Wed Mar 18 20:14:29 GMT 2015 0x9F33D420 generationID_706127423 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generationID_706127423 associated_files_generator ./pll_pal/clk_wiz_v3_6_readme.txt ignore txt Sun Oct 13 18:34:18 GMT 2013 0x5B63DA78 generationID_706127423 ejava_generator ./pll_pal/example_design/pll_pal_exdes.ucf ignore ucf Wed Mar 18 20:14:34 GMT 2015 0x96B868C6 generationID_706127423 ./pll_pal/example_design/pll_pal_exdes.vhd ignore vhdl Wed Mar 18 20:14:34 GMT 2015 0xAC34E26B generationID_706127423 ./pll_pal/example_design/pll_pal_exdes.xdc ignore xdc Wed Mar 18 20:14:34 GMT 2015 0xC6047BF4 generationID_706127423 ./pll_pal/implement/implement.bat ignore unknown Wed Mar 18 20:14:34 GMT 2015 0xC84918A2 generationID_706127423 ./pll_pal/implement/implement.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x29768185 generationID_706127423 ./pll_pal/implement/planAhead_ise.bat ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x6966A508 generationID_706127423 ./pll_pal/implement/planAhead_ise.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x7F8B5943 generationID_706127423 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2015 0x817C1754 generationID_706127423 ./pll_pal/simulation/functional/simulate_mti.bat ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x5620C7DE generationID_706127423 ./pll_pal/simulation/functional/simulate_mti.do ignore unknown Wed Mar 18 20:14:34 GMT 2015 0xD2996AE5 generationID_706127423 ./pll_pal/simulation/functional/simulate_mti.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x08E1E243 generationID_706127423 ./pll_pal/simulation/functional/simulate_ncsim.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x10C555F7 generationID_706127423 ./pll_pal/simulation/functional/simulate_vcs.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x96FB469F generationID_706127423 ./pll_pal/simulation/functional/wave.do ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x9669CD8D generationID_706127423 ./pll_pal/simulation/functional/wave.sv ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x5DA2BE69 generationID_706127423 ./pll_pal/simulation/pll_pal_tb.vhd ignore vhdl Wed Mar 18 20:14:34 GMT 2015 0x62FDED61 generationID_706127423 ./pll_pal/simulation/timing/pll_pal_tb.vhd ignore vhdl Wed Mar 18 20:14:34 GMT 2015 0x1685662D generationID_706127423 ./pll_pal/simulation/timing/sdf_cmd_file ignore unknown Wed Mar 18 20:14:34 GMT 2015 0xA481C77B generationID_706127423 ./pll_pal/simulation/timing/simcmds.tcl ignore tcl Wed Mar 18 20:14:34 GMT 2015 0x28687ACF generationID_706127423 ./pll_pal/simulation/timing/simulate_isim.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0xE7BCE5B1 generationID_706127423 ./pll_pal/simulation/timing/simulate_mti.bat ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x98B4D657 generationID_706127423 ./pll_pal/simulation/timing/simulate_mti.do ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x3569F171 generationID_706127423 ./pll_pal/simulation/timing/simulate_mti.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x9F33D420 generationID_706127423 ./pll_pal/simulation/timing/simulate_ncsim.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0xB38F33B4 generationID_706127423 ./pll_pal/simulation/timing/simulate_vcs.sh ignore unknown Wed Mar 18 20:14:34 GMT 2015 0xDBBDC8C4 generationID_706127423 ./pll_pal/simulation/timing/ucli_commands.key ignore unknown Wed Mar 18 20:14:34 GMT 2015 0x37782F99 generationID_706127423 ./pll_pal/simulation/timing/vcs_session.tcl ignore tcl Wed Mar 18 20:14:34 GMT 2015 0x28340249 generationID_706127423 ./pll_pal/simulation/timing/wave.do ignore unknown Wed Mar 18 20:14:34 GMT 2015 0xA8BF3C37 generationID_706127423 ./pll_pal.ucf ucf Wed Mar 18 20:14:34 GMT 2015 0x2364172F generationID_706127423 ./pll_pal.vhd vhdl Wed Mar 18 20:14:34 GMT 2015 0x9270D714 generationID_706127423 ./pll_pal.vho vho Wed Mar 18 20:14:34 GMT 2015 0x48F05B75 generationID_706127423 ./pll_pal.xdc ignore xdc Wed Mar 18 20:14:34 GMT 2015 0x87C1DCB0 generationID_706127423 ./pll_pal_xmdf.tcl tcl Wed Mar 18 20:14:34 GMT 2015 0xE268409C generationID_706127423 all_documents_generator ./pll_pal/doc/clk_wiz_v3_6_readme.txt ignore txt Wed Mar 18 20:14:39 GMT 2015 0x5B63DA78 generationID_706127423 ./pll_pal/doc/clk_wiz_v3_6_vinfo.html ignore unknown Wed Mar 18 20:14:39 GMT 2015 0xF2E77607 generationID_706127423 ./pll_pal/doc/pg065_clk_wiz.pdf ignore pdf Wed Mar 18 20:14:39 GMT 2015 0xCE1EE896 generationID_706127423 readme_documents_generator asy_generator ./pll_pal.asy asy Wed Mar 18 20:14:41 GMT 2015 0x65D77889 generationID_706127423 ise_generator ./pll_pal.gise ignore gise Wed Mar 18 20:14:44 GMT 2015 0x7C295176 generationID_706127423 ./pll_pal.xise ignore xise Wed Mar 18 20:14:44 GMT 2015 0x80A455E1 generationID_706127423 deliver_readme_generator flist_generator ./pll_pal_flist.txt ignore txtFlist txt Wed Mar 18 20:14:44 GMT 2015 0xA739BEB8 generationID_706127423 view_readme_generator pll_ntsc pll_ntsc true true false false false No_Jitter false false 32 Units_MHz Units_UI REL_PRIMARY 100.000 UI 0.010 0.010 0.010 0.010 312.5 100.0 false false false false false false 1 false false false false false false false CLK_IN1 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE 57.2727 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 100.000 0.000 50.000 false false Single_ended_clock_capable_pin false CLK_IN2 Single_ended_clock_capable_pin BUFG BUFG BUFG BUFG BUFG BUFG BUFG FDBK_AUTO SINGLE CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N lin64 empty true DONE true false false false false false false RESET LOCKED POWER_DOWN CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED false None 1 OPTIMIZED 4.000 0.000 false 10.000 10.000 false false ZHOLD 0.010 0.010 false 4.000 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false 1 0.500 0.000 false false None 2.0 32 5 false 31.250 NONE SYSTEM_SYNCHRONOUS 0 1X false CLKFX CLK0 CLK0 CLK0 CLK0 CLK0 false None 1 4 2 0.000 false 10.000 NONE CLKFX CLKFX CLKFX false None OPTIMIZED 25 0.000 CLKFBOUT 1 31.250 SYSTEM_SYNCHRONOUS 0.010 14 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 1 0.500 0.000 NONE AUTO PLL_BASE MMCM CENTER_HIGH 250 0 0 0 0 0 0 pll_ntsc lin64 1 1 0.010 0.010 No_Jitter 0 0 0 0 0 0 0 0 PLL_BASE 0 32 Units_MHz 100.000 FDBK_AUTO Single_ended_clock_capable_pin Single_ended_clock_capable_pin SINGLE 1 1 0 0 0 0 0 1 BUFG BUFG BUFG BUFG BUFG BUFG BUFG __primary______________32____________0.010 no_secondary_input_clock CLK_OUT1____57.143______0.000______50.0______290.503____196.077 no_CLK_OUT2_output no_CLK_OUT3_output no_CLK_OUT4_output no_CLK_OUT5_output no_CLK_OUT6_output no_CLK_OUT7_output 57.2727 100.000 100.000 100.000 100.000 100.000 100.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 50.000 50.000 50.000 50.000 50.000 50.000 50.000 57.143 N/A N/A N/A N/A N/A N/A 0.000 N/A N/A N/A N/A N/A N/A 50.0 N/A N/A N/A N/A N/A N/A None OPTIMIZED 4.000 10.000 10.000 FALSE FALSE ZHOLD 1 0.010 0.010 FALSE 4.000 1 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 0.000 FALSE FALSE FALSE FALSE FALSE FALSE FALSE FALSE None OPTIMIZED CLKFBOUT 25 31.250 SYSTEM_SYNCHRONOUS 1 0.010 14 1 1 1 1 1 0.500 0.500 0.500 0.500 0.500 0.500 0.000 0.000 0.000 0.000 0.000 0.000 0.000 None 2.000 32 5 FALSE 31.25 NONE 1X BUFG SYSTEM_SYNCHRONOUS 0 FALSE CLKFX NONE NONE NONE NONE NONE None 2 1 4 31.25 0.000 NONE FALSE CLKFX NONE NONE AUTO 0 0 0 0 NONE CLK_IN1 CLK_IN2 CLK_OUT1 CLK_OUT2 CLK_OUT3 CLK_OUT4 CLK_OUT5 CLK_OUT6 CLK_OUT7 RESET LOCKED CLKFB_IN CLKFB_IN_P CLKFB_IN_N CLKFB_OUT CLKFB_OUT_P CLKFB_OUT_N POWER_DOWN DADDR DCLK DRDY DWE DIN DOUT DEN PSCLK PSEN PSINCDEC PSDONE CLK_VALID STATUS CLK_IN_SEL INPUT_CLK_STOPPED CLKFB_STOPPED 312.5 100.0 MMCM CENTER_HIGH 4000 coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -3 BusFormatAngleBracketNotRipped VHDL true Other false false false Ngc false Behavioral VHDL false 2012-05-10+12:44 apply_current_project_options_generator customization_generator model_parameter_resolution_generator ip_xco_generator ./pll_ntsc.xco xco Wed Mar 18 20:16:20 GMT 2015 0x63EDD46E generationID_152152107 tcl_flow_generator ./pll_ntsc/example_design/pll_ntsc_exdes.ucf ignore ucf Wed Mar 18 20:16:25 GMT 2015 0x5C517F47 generationID_152152107 ./pll_ntsc/example_design/pll_ntsc_exdes.vhd ignore vhdl Wed Mar 18 20:16:20 GMT 2015 0xFF0CEFB6 generationID_152152107 ./pll_ntsc/example_design/pll_ntsc_exdes.xdc ignore xdc Wed Mar 18 20:16:25 GMT 2015 0xB02C4D2B generationID_152152107 ./pll_ntsc/implement/implement.bat ignore unknown Wed Mar 18 20:16:25 GMT 2015 0x60DE3FB2 generationID_152152107 ./pll_ntsc/implement/implement.sh ignore unknown Wed Mar 18 20:16:24 GMT 2015 0x5812B4F5 generationID_152152107 ./pll_ntsc/implement/planAhead_ise.bat ignore unknown Wed Mar 18 20:16:24 GMT 2015 0x6966A508 generationID_152152107 ./pll_ntsc/implement/planAhead_ise.sh ignore unknown Wed Mar 18 20:16:24 GMT 2015 0x7F8B5943 generationID_152152107 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20:16:23 GMT 2015 0x715EE4CD generationID_152152107 ./pll_ntsc/simulation/functional/simulate_mti.bat ignore unknown Wed Mar 18 20:16:21 GMT 2015 0x472A6E04 generationID_152152107 ./pll_ntsc/simulation/functional/simulate_mti.do ignore unknown Wed Mar 18 20:16:22 GMT 2015 0x66641E06 generationID_152152107 ./pll_ntsc/simulation/functional/simulate_mti.sh ignore unknown Wed Mar 18 20:16:21 GMT 2015 0xFB0D49E1 generationID_152152107 ./pll_ntsc/simulation/functional/simulate_ncsim.sh ignore unknown Wed Mar 18 20:16:22 GMT 2015 0x0ED75A73 generationID_152152107 ./pll_ntsc/simulation/functional/simulate_vcs.sh ignore unknown Wed Mar 18 20:16:23 GMT 2015 0x95289FF4 generationID_152152107 ./pll_ntsc/simulation/functional/wave.do ignore unknown Wed Mar 18 20:16:22 GMT 2015 0x955DF377 generationID_152152107 ./pll_ntsc/simulation/functional/wave.sv ignore unknown Wed Mar 18 20:16:22 GMT 2015 0x6AE7F9DC generationID_152152107 ./pll_ntsc/simulation/pll_ntsc_tb.vhd ignore vhdl Wed Mar 18 20:16:20 GMT 2015 0x7EACF0C5 generationID_152152107 ./pll_ntsc/simulation/timing/pll_ntsc_tb.vhd ignore vhdl Wed Mar 18 20:16:21 GMT 2015 0x955E7826 generationID_152152107 ./pll_ntsc/simulation/timing/sdf_cmd_file ignore unknown Wed Mar 18 20:16:22 GMT 2015 0xA481C77B generationID_152152107 ./pll_ntsc/simulation/timing/simcmds.tcl ignore tcl Wed Mar 18 20:16:23 GMT 2015 0x21F6523A generationID_152152107 ./pll_ntsc/simulation/timing/simulate_isim.sh ignore unknown Wed Mar 18 20:16:23 GMT 2015 0xD1380B6D generationID_152152107 ./pll_ntsc/simulation/timing/simulate_mti.bat ignore unknown Wed Mar 18 20:16:22 GMT 2015 0x15ADC34C generationID_152152107 ./pll_ntsc/simulation/timing/simulate_mti.do ignore unknown Wed Mar 18 20:16:22 GMT 2015 0xA85EB085 generationID_152152107 ./pll_ntsc/simulation/timing/simulate_mti.sh ignore unknown Wed Mar 18 20:16:21 GMT 2015 0x0A5772CA generationID_152152107 ./pll_ntsc/simulation/timing/simulate_ncsim.sh ignore unknown Wed Mar 18 20:16:22 GMT 2015 0x30AC8765 generationID_152152107 ./pll_ntsc/simulation/timing/simulate_vcs.sh ignore unknown Wed Mar 18 20:16:23 GMT 2015 0x3118AD2E generationID_152152107 ./pll_ntsc/simulation/timing/ucli_commands.key ignore unknown Wed Mar 18 20:16:24 GMT 2015 0x37782F99 generationID_152152107 ./pll_ntsc/simulation/timing/vcs_session.tcl ignore tcl Wed Mar 18 20:16:24 GMT 2015 0x28340249 generationID_152152107 ./pll_ntsc/simulation/timing/wave.do ignore unknown Wed Mar 18 20:16:22 GMT 2015 0x8E02511D generationID_152152107 ./pll_ntsc.ucf ucf Wed Mar 18 20:16:25 GMT 2015 0xA877BC16 generationID_152152107 ./pll_ntsc.vhd vhdl Wed Mar 18 20:16:20 GMT 2015 0x6F17D1D8 generationID_152152107 ./pll_ntsc.vho vho Wed Mar 18 20:16:21 GMT 2015 0x5260F690 generationID_152152107 ./pll_ntsc.xdc ignore xdc Wed Mar 18 20:16:25 GMT 2015 0x4C104C73 generationID_152152107 ./pll_ntsc_xmdf.tcl tcl Wed Mar 18 20:16:21 GMT 2015 0xB2B77287 generationID_152152107 associated_files_generator ./pll_ntsc/clk_wiz_v3_6_readme.txt ignore txt Sun Oct 13 18:34:18 GMT 2013 0x5B63DA78 generationID_152152107 ejava_generator ./pll_ntsc/example_design/pll_ntsc_exdes.ucf ignore ucf Wed Mar 18 20:16:26 GMT 2015 0x5C517F47 generationID_152152107 ./pll_ntsc/example_design/pll_ntsc_exdes.vhd ignore vhdl Wed Mar 18 20:16:26 GMT 2015 0xFF0CEFB6 generationID_152152107 ./pll_ntsc/example_design/pll_ntsc_exdes.xdc ignore xdc Wed Mar 18 20:16:26 GMT 2015 0xB02C4D2B generationID_152152107 ./pll_ntsc/implement/implement.bat ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x60DE3FB2 generationID_152152107 ./pll_ntsc/implement/implement.sh ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x5812B4F5 generationID_152152107 ./pll_ntsc/implement/planAhead_ise.bat ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x6966A508 generationID_152152107 ./pll_ntsc/implement/planAhead_ise.sh ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x7F8B5943 generationID_152152107 ./pll_ntsc/implement/planAhead_ise.tcl ignore tcl Wed Mar 18 20:16:26 GMT 2015 0x19A277EB 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./pll_ntsc/simulation/timing/pll_ntsc_tb.vhd ignore vhdl Wed Mar 18 20:16:26 GMT 2015 0x955E7826 generationID_152152107 ./pll_ntsc/simulation/timing/sdf_cmd_file ignore unknown Wed Mar 18 20:16:26 GMT 2015 0xA481C77B generationID_152152107 ./pll_ntsc/simulation/timing/simcmds.tcl ignore tcl Wed Mar 18 20:16:26 GMT 2015 0x21F6523A generationID_152152107 ./pll_ntsc/simulation/timing/simulate_isim.sh ignore unknown Wed Mar 18 20:16:26 GMT 2015 0xD1380B6D generationID_152152107 ./pll_ntsc/simulation/timing/simulate_mti.bat ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x15ADC34C generationID_152152107 ./pll_ntsc/simulation/timing/simulate_mti.do ignore unknown Wed Mar 18 20:16:26 GMT 2015 0xA85EB085 generationID_152152107 ./pll_ntsc/simulation/timing/simulate_mti.sh ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x0A5772CA generationID_152152107 ./pll_ntsc/simulation/timing/simulate_ncsim.sh ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x30AC8765 generationID_152152107 ./pll_ntsc/simulation/timing/simulate_vcs.sh ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x3118AD2E generationID_152152107 ./pll_ntsc/simulation/timing/ucli_commands.key ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x37782F99 generationID_152152107 ./pll_ntsc/simulation/timing/vcs_session.tcl ignore tcl Wed Mar 18 20:16:26 GMT 2015 0x28340249 generationID_152152107 ./pll_ntsc/simulation/timing/wave.do ignore unknown Wed Mar 18 20:16:26 GMT 2015 0x8E02511D generationID_152152107 ./pll_ntsc.ucf ucf Wed Mar 18 20:16:26 GMT 2015 0xA877BC16 generationID_152152107 ./pll_ntsc.vhd vhdl Wed Mar 18 20:16:26 GMT 2015 0x6F17D1D8 generationID_152152107 ./pll_ntsc.vho vho Wed Mar 18 20:16:26 GMT 2015 0x5260F690 generationID_152152107 ./pll_ntsc.xdc ignore xdc Wed Mar 18 20:16:26 GMT 2015 0x4C104C73 generationID_152152107 ./pll_ntsc_xmdf.tcl tcl Wed Mar 18 20:16:26 GMT 2015 0xB2B77287 generationID_152152107 all_documents_generator ./pll_ntsc/doc/clk_wiz_v3_6_readme.txt ignore txt Wed Mar 18 20:16:31 GMT 2015 0x5B63DA78 generationID_152152107 ./pll_ntsc/doc/clk_wiz_v3_6_vinfo.html ignore unknown Wed Mar 18 20:16:31 GMT 2015 0xF2E77607 generationID_152152107 ./pll_ntsc/doc/pg065_clk_wiz.pdf ignore pdf Wed Mar 18 20:16:31 GMT 2015 0xCE1EE896 generationID_152152107 readme_documents_generator asy_generator ./pll_ntsc.asy asy Wed Mar 18 20:16:34 GMT 2015 0x9F56212D generationID_152152107 ise_generator ./pll_ntsc.gise ignore gise Wed Mar 18 20:16:37 GMT 2015 0x8BFDA800 generationID_152152107 ./pll_ntsc.xise ignore xise Wed Mar 18 20:16:37 GMT 2015 0x1CED7299 generationID_152152107 deliver_readme_generator flist_generator ./pll_ntsc_flist.txt ignore txtFlist txt Wed Mar 18 20:16:37 GMT 2015 0xC29027ED generationID_152152107 view_readme_generator coregen ./ ./tmp/ ./tmp/_cg/ xc6slx9 spartan6 tqg144 -3 BusFormatAngleBracketNotRipped VHDL true Other false false false Ngc false Behavioral VHDL false