clk_a
clk_a
reset_n
reset_n
sdram_rdy
sdram_rdy
sdram_cs_n
sdram_cs_n
sdram_ras_n
sdram_ras_n
sdram_cas_n
sdram_cas_n
sdram_we_n
sdram_we_n
sdram_dqm_n[1:0]
sdram_dqm_n[1:0]
HEXRADIX
sdram_ba[1:0]
sdram_ba[1:0]
HEXRADIX
sdram_addr[11:0]
sdram_addr[11:0]
HEXRADIX
sdram_dq_oe
sdram_dq_oe
sdram_dq_o[15:0]
sdram_dq_o[15:0]
HEXRADIX
sdram_dq_i[15:0]
sdram_dq_i[15:0]
HEXRADIX
seq_reg[11:0]
seq_reg[11:0]
HEXRADIX
seq_ph_reg
seq_ph_reg
ram_rd_active[2:0]
ram_rd_active[2:0]
ram_wr_active[2:0]
ram_wr_active[2:0]
ref_reg
ref_reg
r_refr_req
r_refr_req
r_psel[2:0]
r_psel[2:0]
ram_di[15:0]
ram_di[15:0]
HEXRADIX
ram_di2[15:0]
ram_di2[15:0]
HEXRADIX
ram_do[15:0]
ram_do[15:0]
HEXRADIX
true
#0000ff
ram_do2[15:0]
ram_do2[15:0]
HEXRADIX
true
#0000ff