reset_n reset_n reset reset sdram_ba[1:0] sdram_ba[1:0] HEXRADIX sdram_cs_n sdram_cs_n sdram_ras_n sdram_ras_n sdram_cas_n sdram_cas_n sdram_we_n sdram_we_n sdram_dqm_n[1:0] sdram_dqm_n[1:0] HEXRADIX sdram_clk sdram_clk sdram_a[12:0] sdram_a[12:0] HEXRADIX sdram_dq[15:0] sdram_dq[15:0] HEXRADIX reset reset di[7:0] di[7:0] HEXRADIX do[7:0] do[7:0] HEXRADIX a[15:0] a[15:0] HEXRADIX throttle throttle memory_ready memory_ready sdram_request sdram_request sdram_request_next sdram_request_next sdram_request_reg sdram_request_reg sdram_request_complete_next sdram_request_complete_next sdram_request_complete_reg sdram_request_complete_reg sdram_request_complete sdram_request_complete sdram_rdy sdram_rdy sdram_addr[22:0] sdram_addr[22:0] HEXRADIX cpu_fetch cpu_fetch antic_fetch antic_fetch ap1_rden ap1_rden ap1_wren ap1_wren ram_rd_active ram_rd_active ram_wr_active ram_wr_active seq_ph_reg seq_ph_reg seq_reg[11:0] seq_reg[11:0] sd_dat0 sd_dat0 sd_clk sd_clk sd_cmd sd_cmd sd_dat3 sd_dat3 clock clock reset_n reset_n enable enable cpol cpol cpha cpha cont cont clk_div clk_div addr addr tx_data[7:0] tx_data[7:0] HEXRADIX miso miso mosi mosi busy busy rx_data[7:0] rx_data[7:0] HEXRADIX