phi0 phi0 rst_n rst_n clk_slow clk_slow rdy rdy halt_n halt_n nmi_n nmi_n irq_n irq_n s0 s0 clk_out clk_out a[15:0] a[15:0] HEXRADIX w_n w_n sync sync syncphi2 syncphi2 initmode initmode phi1 phi1 phi2 phi2 halt_n halt_n request_handling_reg request_handling_reg bus_subcycle[4:0] bus_subcycle[4:0] d[7:0] d[7:0] HEXRADIX clk clk reset reset enable enable di[7:0] di[7:0] HEXRADIX irq_n irq_n nmi_n nmi_n memory_ready memory_ready throttle throttle rdy rdy do[7:0] do[7:0] HEXRADIX a[15:0] a[15:0] HEXRADIX r_w_n r_w_n cpu_fetch cpu_fetch thecpucycle thecpucycle theopcode[7:0] theopcode[7:0] HEXRADIX slave_addr[15:0] slave_addr[15:0] HEXRADIX slave_data_out[7:0] slave_data_out[7:0] HEXRADIX slave_data_in[7:0] slave_data_in[7:0] HEXRADIX slave_request slave_request