clkout clkout phi2 phi2 inclk0 inclk0 c0 c0 locked locked bus_phi2 bus_phi2 clk clk enable_179 enable_179 addr[3:0] addr[3:0] HEXRADIX data_in[7:0] data_in[7:0] HEXRADIX wr_en wr_en data_out[7:0] data_out[7:0] HEXRADIX enable_cycle enable_cycle enable_179 enable_179 count_reg[7:0] count_reg[7:0] HEXRADIX channel_0_out[3:0] channel_0_out[3:0] HEXRADIX channel_1_out[3:0] channel_1_out[3:0] HEXRADIX channel_2_out[3:0] channel_2_out[3:0] HEXRADIX channel_3_out[3:0] channel_3_out[3:0] HEXRADIX pbi_write_enable pbi_write_enable pbi_addr_out[15:0] pbi_addr_out[15:0] HEXRADIX cart_data_write[7:0] cart_data_write[7:0] HEXRADIX data_in[7:0] data_in[7:0] HEXRADIX bus_data_out[7:0] bus_data_out[7:0] HEXRADIX bus_data_oe bus_data_oe request request phi2 phi2 clk_slow clk_slow a[4:0] a[4:0] d[7:0] d[7:0] HEXRADIX state_reg[2:0] state_reg[2:0] delay_reg[31:0] delay_reg[31:0] HEXRADIX w_n w_n control_n_in[0:0] control_n_in[0:0] bus_control_n[0:0] bus_control_n[0:0] bus_cs_n bus_cs_n cs_comb cs_comb bus_data_out[7:0] bus_data_out[7:0] HEXRADIX internal_memory_request internal_memory_request bus_drive bus_drive bus_request bus_request addr_in[4:0] addr_in[4:0] data_in[7:0] data_in[7:0] HEXRADIX rw_n rw_n bus_control_n[0:0] bus_control_n[0:0] bus_cs bus_cs cs cs do_mux[7:0] do_mux[7:0] HEXRADIX [4] aud[4] [3] aud[3] [2] aud[2] [1] aud[1] volume_out_l[15:0] volume_out_l[15:0] HEXRADIX volume_out_r[15:0] volume_out_r[15:0] HEXRADIX clk clk enable_179 enable_179 channel_l_0[3:0] channel_l_0[3:0] channel_l_1[3:0] channel_l_1[3:0] channel_l_2[3:0] channel_l_2[3:0] channel_l_3[3:0] channel_l_3[3:0] covox_channel_l_0[7:0] covox_channel_l_0[7:0] covox_channel_l_1[7:0] covox_channel_l_1[7:0] channel_r_0[3:0] channel_r_0[3:0] channel_r_1[3:0] channel_r_1[3:0] channel_r_2[3:0] channel_r_2[3:0] channel_r_3[3:0] channel_r_3[3:0] covox_channel_r_0[7:0] covox_channel_r_0[7:0] covox_channel_r_1[7:0] covox_channel_r_1[7:0] gtia_sound gtia_sound sio_audio[7:0] sio_audio[7:0] audio_in[15:0] audio_in[15:0] sample_in sample_in audio_in[15:0] audio_in[15:0] HEXRADIX left_channel_reg left_channel_reg sample_in sample_in iox_sda iox_sda iox_scl iox_scl ena ena addr[6:0] addr[6:0] HEXRADIX rw rw data_wr[7:0] data_wr[7:0] HEXRADIX busy busy busy_reg busy_reg op_complete op_complete state_reg[3:0] state_reg[3:0] ena ena data_wr[7:0] data_wr[7:0] HEXRADIX i2c_state_reg[1:0] i2c_state_reg[1:0] scl scl sda sda read_req read_req data_to_master[7:0] data_to_master[7:0] HEXRADIX data_valid data_valid data_from_master[7:0] data_from_master[7:0] HEXRADIX state_reg state_reg sda_prev_reg sda_prev_reg scl_prev_reg scl_prev_reg scl_debounced scl_debounced sda_debounced sda_debounced start_reg start_reg stop_reg stop_reg keyboard_response_reg[1:0] keyboard_response_reg[1:0] keyboard_scan[5:0] keyboard_scan[5:0] HEXRADIX keyboard_scan_reg[5:0] keyboard_scan_reg[5:0] HEXRADIX keyboard_response[1:0] keyboard_response[1:0]