/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 2018  Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors.  Please
refer to the applicable agreement for further details.
*/
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(symbol
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	(text "int_osc" (rect 59 -1 87 11)(font "Arial" (font_size 10)))
	(text "inst" (rect 8 88 20 100)(font "Arial" ))
	(port
		(pt 0 72)
		(input)
		(text "oscena" (rect 0 0 28 12)(font "Arial" (font_size 8)))
		(text "oscena" (rect 4 61 40 72)(font "Arial" (font_size 8)))
		(line (pt 0 72)(pt 48 72)(line_width 1))
	)
	(port
		(pt 160 72)
		(output)
		(text "clkout" (rect 0 0 22 12)(font "Arial" (font_size 8)))
		(text "clkout" (rect 130 61 166 72)(font "Arial" (font_size 8)))
		(line (pt 160 72)(pt 112 72)(line_width 1))
	)
	(drawing
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		(text "clk" (rect 97 67 212 144)(font "Arial" (color 0 0 0)))
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		(text "oscena" (rect 53 67 142 144)(font "Arial" (color 0 0 0)))
		(text " int_osc " (rect 126 88 306 186)(font "Arial" ))
		(line (pt 48 32)(pt 112 32)(line_width 1))
		(line (pt 112 32)(pt 112 88)(line_width 1))
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)