# -------------------------------------------------------------------------- # # # Copyright (C) 2017 Intel Corporation. All rights reserved. # Your use of Intel Corporation's design tools, logic functions # and other software and tools, and its AMPP partner logic # functions, and any output files from any of the foregoing # (including device programming or simulation files), and any # associated documentation or information are expressly subject # to the terms and conditions of the Intel Program License # Subscription Agreement, the Intel Quartus Prime License Agreement, # the Intel MegaCore Function License Agreement, or other # applicable license agreement, including, without limitation, # that your use is for the sole purpose of programming logic # devices manufactured by Intel and sold by Intel or its # authorized distributors. Please refer to the applicable # agreement for further details. # # -------------------------------------------------------------------------- # # # Quartus Prime # Version 17.0.0 Build 595 04/25/2017 SJ Lite Edition # Date created = 19:35:48 June 01, 2018 # # -------------------------------------------------------------------------- # # # Notes: # # 1) The default values for assignments are stored in the file: # anticmax_assignment_defaults.qdf # If this file doesn't exist, see file: # assignment_defaults.qdf # # 2) Altera recommends that you do not modify this file. This # file is updated automatically by the Quartus Prime software # and any changes you make may be lost or overwritten. # # -------------------------------------------------------------------------- # set_global_assignment -name FAMILY "MAX 10" set_global_assignment -name DEVICE 10M02SCU169C8G set_global_assignment -name TOP_LEVEL_ENTITY anticmax set_global_assignment -name ORIGINAL_QUARTUS_VERSION 17.0.0 set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:35:48 JUNE 01, 2018" set_global_assignment -name LAST_QUARTUS_VERSION "18.0.0 Lite Edition" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PACKAGE UFBGA set_global_assignment -name DEVICE_FILTER_PIN_COUNT 169 set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 256 #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_RST #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_INT #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_SDA #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to IOX_SCL # #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[0] #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[1] #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[2] #set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PADDLE[3] set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to REF_N set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to REF_N_B set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HALT_N set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to HALT_N_B set_instance_assignment -name CURRENT_STRENGTH_NEW "4MA" -to REF_N set_instance_assignment -name CURRENT_STRENGTH_NEW "4MA" -to HALT_N # #set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[1] #set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[2] #set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[3] #set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to AUD[4] set_location_assignment PIN_G9 -to CLK_SLOW set_location_assignment PIN_H8 -to CLK_OUT set_location_assignment PIN_A6 -to NC[1] #PIN1 (VSS) set_location_assignment PIN_B5 -to AN[0] #PIN2 set_location_assignment PIN_A5 -to AN[1] #PIN3 set_location_assignment PIN_B4 -to LP_N #PIN4 set_location_assignment PIN_A4 -to AN[2] #PIN5 set_location_assignment PIN_B3 -to RNMI_N #PIN6 set_location_assignment PIN_A3 -to NMI_N #PIN7 set_location_assignment PIN_C1 -to REF_N #PIN8 set_location_assignment PIN_D1 -to REF_N_B #PIN8 set_location_assignment PIN_A2 -to HALT_N #PIN9 set_location_assignment PIN_B2 -to HALT_N_B #PIN9 set_location_assignment PIN_B1 -to A[3] #PIN10 set_location_assignment PIN_M1 -to A[2] #PIN11 set_location_assignment PIN_M2 -to A[1] #PIN12 set_location_assignment PIN_N2 -to A[0] #PIN13 set_location_assignment PIN_L3 -to RW_N #PIN14 set_location_assignment PIN_M3 -to RDY #PIN15 set_location_assignment PIN_N3 -to RDY_B #PIN15 set_location_assignment PIN_K5 -to RDY_C #PIN15 set_location_assignment PIN_M4 -to A[10] #PIN16 set_location_assignment PIN_N4 -to A[12] #PIN17 set_location_assignment PIN_M5 -to A[13] #PIN18 set_location_assignment PIN_N5 -to A[14] #PIN19 set_location_assignment PIN_N6 -to A[15] #PIN20 set_location_assignment PIN_M7 -to NC[2] #PIN21 (VCC) set_location_assignment PIN_N7 -to A[11] #PIN22 set_location_assignment PIN_M8 -to A[9] #PIN23 set_location_assignment PIN_N8 -to A[8] #PIN24 set_location_assignment PIN_M9 -to A[7] #PIN25 set_location_assignment PIN_N9 -to A[6] #PIN26 set_location_assignment PIN_M10 -to A[5] #PIN27 set_location_assignment PIN_N10 -to A[4] #PIN28 set_location_assignment PIN_M11 -to PHI2 #PIN29 set_location_assignment PIN_N11 -to D[0] #PIN30 set_location_assignment PIN_A12 -to D[1] #PIN31 set_location_assignment PIN_B11 -to D[2] #PIN32 set_location_assignment PIN_A11 -to D[3] #PIN33 set_location_assignment PIN_B10 -to PHI0 #PIN34 set_location_assignment PIN_A10 -to FO0 #PIN35 set_location_assignment PIN_A9 -to RST_N #PIN36 set_location_assignment PIN_A8 -to D[7] #PIN37 set_location_assignment PIN_B7 -to D[6] #PIN38 set_location_assignment PIN_A7 -to D[5] #PIN39 set_location_assignment PIN_B6 -to D[4] #PIN40 set_location_assignment PIN_L13 -to GPIO[0] #JP1_1 set_location_assignment PIN_M13 -to GPIO[1] #JP1_2 set_location_assignment PIN_N12 -to GPIO[2] #JP1_3 set_location_assignment PIN_K13 -to GPIO[3] #JP2_1 set_location_assignment PIN_K12 -to GPIO[4] #JP2_2 set_location_assignment PIN_L12 -to GPIO[5] #JP2_3 set_location_assignment PIN_C13 -to GPIO[6] #JP3_1 set_location_assignment PIN_D12 -to GPIO[7] #JP3_2 set_location_assignment PIN_D13 -to GPIO[8] #JP3_3 set_location_assignment PIN_B12 -to GPIO[9] #JP4_1 set_location_assignment PIN_B13 -to GPIO[10] #JP4_2 set_location_assignment PIN_C12 -to GPIO[11] #JP4_3 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER ON set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE "12.5 %" set_global_assignment -name ENABLE_OCT_DONE OFF set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "PASSIVE SERIAL" set_global_assignment -name USE_CONFIGURATION_DEVICE ON set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall set_global_assignment -name ENABLE_SIGNALTAP ON set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp set_instance_assignment -name CURRENT_STRENGTH_NEW "MINIMUM CURRENT" -to CLK_OUT set_global_assignment -name OPTIMIZATION_MODE BALANCED set_global_assignment -name VHDL_FILE generic_ram_infer.vhdl set_global_assignment -name VHDL_FILE simple_counter.vhdl set_global_assignment -name VHDL_FILE wide_delay_line.vhdl set_global_assignment -name VHDL_FILE antic_dma_clock.vhdl set_global_assignment -name VHDL_FILE antic_counter.vhdl set_global_assignment -name VHDL_FILE antic.vhdl set_global_assignment -name VHDL_FILE timing_antic.vhd set_global_assignment -name SDC_FILE anticmax.sdc set_global_assignment -name VHDL_FILE complete_address_decoder.vhdl set_global_assignment -name VHDL_FILE syncreset_enable_divider.vhd set_global_assignment -name VHDL_FILE delay_line.vhdl set_global_assignment -name VHDL_FILE latch_delay_line.vhdl set_global_assignment -name VHDL_FILE phi_mult.vhdl set_global_assignment -name VHDL_FILE synchronizer.vhdl set_global_assignment -name VHDL_FILE anticmax.vhd set_global_assignment -name QIP_FILE int_osc/synthesis/int_osc.qip set_global_assignment -name QIP_FILE pll.qip set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top