atarixlfpga_svn - Revision 1513: /branches/trunkv37/atari_800xl/vampire_v4sa_atari800xl/ddr3/synthesis/submodules

• ..
• altdq_dqs2_acv_connect_to_hard_phy_cyclonev.sv
• altera_avalon_dc_fifo.sdc
• altera_avalon_dc_fifo.v
• altera_avalon_mm_clock_crossing_bridge.v
• altera_avalon_sc_fifo.v
• altera_avalon_st_clock_crosser.v
• altera_avalon_st_handshake_clock_crosser.sdc
• altera_avalon_st_handshake_clock_crosser.v
• altera_avalon_st_pipeline_base.v
• altera_dcfifo_synchronizer_bundle.v
• altera_mem_if_dll_cyclonev.sv
• altera_mem_if_hard_memory_controller_top_cyclonev.sv
• altera_mem_if_oct_cyclonev.sv
• altera_mem_if_sequencer_cpu_cv_synth_cpu_inst.v
• altera_mem_if_sequencer_cpu_cv_synth_cpu_inst_test_bench.v
• altera_mem_if_sequencer_mem_no_ifdef_params.sv
• altera_mem_if_sequencer_rst.sv
• altera_mem_if_simple_avalon_mm_bridge.sv
• altera_merlin_address_alignment.sv
• altera_merlin_arbitrator.sv
• altera_merlin_burst_uncompressor.sv
• altera_merlin_master_agent.sv
• altera_merlin_master_translator.sv
• altera_merlin_slave_agent.sv
• altera_merlin_slave_translator.sv
• altera_merlin_width_adapter.sv
• altera_reset_controller.sdc
• altera_reset_controller.v
• altera_reset_synchronizer.v
• altera_std_synchronizer_nocut.v
• ddr3_mem_if_ddr3_emif_0.v
• ddr3_mem_if_ddr3_emif_0_p0.ppf
• ddr3_mem_if_ddr3_emif_0_p0.sdc
• ddr3_mem_if_ddr3_emif_0_p0.sv
• ddr3_mem_if_ddr3_emif_0_p0_acv_hard_addr_cmd_pads.v
• ddr3_mem_if_ddr3_emif_0_p0_acv_hard_io_pads.v
• ddr3_mem_if_ddr3_emif_0_p0_acv_hard_memphy.v
• ddr3_mem_if_ddr3_emif_0_p0_acv_ldc.v
• ddr3_mem_if_ddr3_emif_0_p0_altdqdqs.v
• ddr3_mem_if_ddr3_emif_0_p0_clock_pair_generator.v
• ddr3_mem_if_ddr3_emif_0_p0_generic_ddio.v
• ddr3_mem_if_ddr3_emif_0_p0_iss_probe.v
• ddr3_mem_if_ddr3_emif_0_p0_parameters.tcl
• ddr3_mem_if_ddr3_emif_0_p0_phy_csr.sv
• ddr3_mem_if_ddr3_emif_0_p0_pin_assignments.tcl
• ddr3_mem_if_ddr3_emif_0_p0_pin_map.tcl
• ddr3_mem_if_ddr3_emif_0_p0_report_timing.tcl
• ddr3_mem_if_ddr3_emif_0_p0_report_timing_core.tcl
• ddr3_mem_if_ddr3_emif_0_p0_reset.v
• ddr3_mem_if_ddr3_emif_0_p0_reset_sync.v
• ddr3_mem_if_ddr3_emif_0_p0_timing.tcl
• ddr3_mem_if_ddr3_emif_0_pll0.sv
• ddr3_mem_if_ddr3_emif_0_s0.v
• ddr3_mem_if_ddr3_emif_0_s0_AC_ROM.hex
• ddr3_mem_if_ddr3_emif_0_s0_inst_ROM.hex
• ddr3_mem_if_ddr3_emif_0_s0_irq_mapper.sv
• ddr3_mem_if_ddr3_emif_0_s0_make_qsys_seq.tcl
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0.v
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter.v
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_demux_001.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_cmd_mux_001.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_001.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_002.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_router_003.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_demux_001.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux.sv
• ddr3_mem_if_ddr3_emif_0_s0_mm_interconnect_0_rsp_mux_001.sv
• ddr3_mem_if_ddr3_emif_0_s0_sequencer_mem.hex
• ddr3_mem_if_ddr3_emif_0_s0_software/
• ddr3_mm_interconnect_0.v
• ddr3_mm_interconnect_0_avalon_st_adapter.v
• ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv
• ddr3_mm_interconnect_0_cmd_demux.sv
• ddr3_mm_interconnect_0_cmd_mux.sv
• ddr3_mm_interconnect_0_router.sv
• ddr3_mm_interconnect_0_router_001.sv
• ddr3_mm_interconnect_0_rsp_demux.sv
• ddr3_mm_interconnect_0_rsp_mux.sv
• sequencer_reg_file.sv
• sequencer_scc_acv_phase_decode.v
• sequencer_scc_acv_wrapper.sv
• sequencer_scc_mgr.sv
• sequencer_scc_reg_file.v
• sequencer_scc_siii_phase_decode.v
• sequencer_scc_siii_wrapper.sv
• sequencer_scc_sv_phase_decode.v
• sequencer_scc_sv_wrapper.sv