-- ddr3.vhd -- Generated using ACDS version 23.1 993 library IEEE; use IEEE.std_logic_1164.all; use IEEE.numeric_std.all; entity ddr3 is port ( clkatari_clk : in std_logic := '0'; -- clkatari.clk ddrext_mem_a : out std_logic_vector(14 downto 0); -- ddrext.mem_a ddrext_mem_ba : out std_logic_vector(2 downto 0); -- .mem_ba ddrext_mem_ck : out std_logic_vector(0 downto 0); -- .mem_ck ddrext_mem_ck_n : out std_logic_vector(0 downto 0); -- .mem_ck_n ddrext_mem_cke : out std_logic_vector(0 downto 0); -- .mem_cke ddrext_mem_cs_n : out std_logic_vector(0 downto 0); -- .mem_cs_n ddrext_mem_dm : out std_logic_vector(1 downto 0); -- .mem_dm ddrext_mem_ras_n : out std_logic_vector(0 downto 0); -- .mem_ras_n ddrext_mem_cas_n : out std_logic_vector(0 downto 0); -- .mem_cas_n ddrext_mem_we_n : out std_logic_vector(0 downto 0); -- .mem_we_n ddrext_mem_reset_n : out std_logic; -- .mem_reset_n ddrext_mem_dq : inout std_logic_vector(15 downto 0) := (others => '0'); -- .mem_dq ddrext_mem_dqs : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs ddrext_mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => '0'); -- .mem_dqs_n ddrext_mem_odt : out std_logic_vector(0 downto 0); -- .mem_odt ddrint_waitrequest : out std_logic; -- ddrint.waitrequest ddrint_readdata : out std_logic_vector(31 downto 0); -- .readdata ddrint_readdatavalid : out std_logic; -- .readdatavalid ddrint_burstcount : in std_logic_vector(0 downto 0) := (others => '0'); -- .burstcount ddrint_writedata : in std_logic_vector(31 downto 0) := (others => '0'); -- .writedata ddrint_address : in std_logic_vector(26 downto 0) := (others => '0'); -- .address ddrint_write : in std_logic := '0'; -- .write ddrint_read : in std_logic := '0'; -- .read ddrint_byteenable : in std_logic_vector(3 downto 0) := (others => '0'); -- .byteenable ddrint_debugaccess : in std_logic := '0'; -- .debugaccess ddroct_rzqin : in std_logic := '0'; -- ddroct.rzqin ddrpll_pll_mem_clk : out std_logic; -- ddrpll.pll_mem_clk ddrpll_pll_write_clk : out std_logic; -- .pll_write_clk ddrpll_pll_locked : out std_logic; -- .pll_locked ddrpll_pll_write_clk_pre_phy_clk : out std_logic; -- .pll_write_clk_pre_phy_clk ddrpll_pll_addr_cmd_clk : out std_logic; -- .pll_addr_cmd_clk ddrpll_pll_avl_clk : out std_logic; -- .pll_avl_clk ddrpll_pll_config_clk : out std_logic; -- .pll_config_clk ddrpll_pll_mem_phy_clk : out std_logic; -- .pll_mem_phy_clk ddrpll_afi_phy_clk : out std_logic; -- .afi_phy_clk ddrpll_pll_avl_phy_clk : out std_logic; -- .pll_avl_phy_clk ddrrefclk_clk : in std_logic := '0'; -- ddrrefclk.clk ddrrefresh_local_refresh_req : in std_logic := '0'; -- ddrrefresh.local_refresh_req ddrrefresh_local_refresh_chip : in std_logic_vector(0 downto 0) := (others => '0'); -- .local_refresh_chip ddrrefresh_local_refresh_ack : out std_logic; -- .local_refresh_ack ddrstatus_local_init_done : out std_logic; -- ddrstatus.local_init_done ddrstatus_local_cal_success : out std_logic; -- .local_cal_success ddrstatus_local_cal_fail : out std_logic; -- .local_cal_fail refresh_clk_clk : out std_logic; -- refresh_clk.clk reset_n_reset_n : in std_logic := '0'; -- reset_n.reset_n softreset_n_reset_n : in std_logic := '0' -- softreset_n.reset_n ); end entity ddr3; architecture rtl of ddr3 is component ddr3_mem_if_ddr3_emif_0 is port ( pll_ref_clk : in std_logic := 'X'; -- clk global_reset_n : in std_logic := 'X'; -- reset_n soft_reset_n : in std_logic := 'X'; -- reset_n afi_clk : out std_logic; -- clk afi_half_clk : out std_logic; -- clk afi_reset_n : out std_logic; -- reset_n afi_reset_export_n : out std_logic; -- reset_n mem_a : out std_logic_vector(14 downto 0); -- mem_a mem_ba : out std_logic_vector(2 downto 0); -- mem_ba mem_ck : out std_logic_vector(0 downto 0); -- mem_ck mem_ck_n : out std_logic_vector(0 downto 0); -- mem_ck_n mem_cke : out std_logic_vector(0 downto 0); -- mem_cke mem_cs_n : out std_logic_vector(0 downto 0); -- mem_cs_n mem_dm : out std_logic_vector(1 downto 0); -- mem_dm mem_ras_n : out std_logic_vector(0 downto 0); -- mem_ras_n mem_cas_n : out std_logic_vector(0 downto 0); -- mem_cas_n mem_we_n : out std_logic_vector(0 downto 0); -- mem_we_n mem_reset_n : out std_logic; -- mem_reset_n mem_dq : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq mem_dqs : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs mem_dqs_n : inout std_logic_vector(1 downto 0) := (others => 'X'); -- mem_dqs_n mem_odt : out std_logic_vector(0 downto 0); -- mem_odt avl_ready_0 : out std_logic; -- waitrequest_n avl_burstbegin_0 : in std_logic := 'X'; -- beginbursttransfer avl_addr_0 : in std_logic_vector(26 downto 0) := (others => 'X'); -- address avl_rdata_valid_0 : out std_logic; -- readdatavalid avl_rdata_0 : out std_logic_vector(31 downto 0); -- readdata avl_wdata_0 : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata avl_be_0 : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable avl_read_req_0 : in std_logic := 'X'; -- read avl_write_req_0 : in std_logic := 'X'; -- write avl_size_0 : in std_logic_vector(2 downto 0) := (others => 'X'); -- burstcount mp_cmd_clk_0_clk : in std_logic := 'X'; -- clk mp_cmd_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n mp_rfifo_clk_0_clk : in std_logic := 'X'; -- clk mp_rfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n mp_wfifo_clk_0_clk : in std_logic := 'X'; -- clk mp_wfifo_reset_n_0_reset_n : in std_logic := 'X'; -- reset_n local_init_done : out std_logic; -- local_init_done local_cal_success : out std_logic; -- local_cal_success local_cal_fail : out std_logic; -- local_cal_fail local_refresh_req : in std_logic := 'X'; -- local_refresh_req local_refresh_chip : in std_logic_vector(0 downto 0) := (others => 'X'); -- local_refresh_chip local_refresh_ack : out std_logic; -- local_refresh_ack oct_rzqin : in std_logic := 'X'; -- rzqin pll_mem_clk : out std_logic; -- pll_mem_clk pll_write_clk : out std_logic; -- pll_write_clk pll_locked : out std_logic; -- pll_locked pll_write_clk_pre_phy_clk : out std_logic; -- pll_write_clk_pre_phy_clk pll_addr_cmd_clk : out std_logic; -- pll_addr_cmd_clk pll_avl_clk : out std_logic; -- pll_avl_clk pll_config_clk : out std_logic; -- pll_config_clk pll_mem_phy_clk : out std_logic; -- pll_mem_phy_clk afi_phy_clk : out std_logic; -- afi_phy_clk pll_avl_phy_clk : out std_logic -- pll_avl_phy_clk ); end component ddr3_mem_if_ddr3_emif_0; component altera_avalon_mm_clock_crossing_bridge is generic ( DATA_WIDTH : integer := 32; SYMBOL_WIDTH : integer := 8; HDL_ADDR_WIDTH : integer := 10; BURSTCOUNT_WIDTH : integer := 1; COMMAND_FIFO_DEPTH : integer := 4; RESPONSE_FIFO_DEPTH : integer := 4; MASTER_SYNC_DEPTH : integer := 2; SLAVE_SYNC_DEPTH : integer := 2 ); port ( m0_clk : in std_logic := 'X'; -- clk m0_reset : in std_logic := 'X'; -- reset s0_clk : in std_logic := 'X'; -- clk s0_reset : in std_logic := 'X'; -- reset s0_waitrequest : out std_logic; -- waitrequest s0_readdata : out std_logic_vector(31 downto 0); -- readdata s0_readdatavalid : out std_logic; -- readdatavalid s0_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount s0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata s0_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address s0_write : in std_logic := 'X'; -- write s0_read : in std_logic := 'X'; -- read s0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable s0_debugaccess : in std_logic := 'X'; -- debugaccess m0_waitrequest : in std_logic := 'X'; -- waitrequest m0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata m0_readdatavalid : in std_logic := 'X'; -- readdatavalid m0_burstcount : out std_logic_vector(0 downto 0); -- burstcount m0_writedata : out std_logic_vector(31 downto 0); -- writedata m0_address : out std_logic_vector(26 downto 0); -- address m0_write : out std_logic; -- write m0_read : out std_logic; -- read m0_byteenable : out std_logic_vector(3 downto 0); -- byteenable m0_debugaccess : out std_logic -- debugaccess ); end component altera_avalon_mm_clock_crossing_bridge; component ddr3_mm_interconnect_0 is port ( clk_1_clk_clk : in std_logic := 'X'; -- clk mem_if_ddr3_emif_0_afi_half_clk_clk : in std_logic := 'X'; -- clk mem_if_ddr3_emif_0_avl_0_translator_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset mem_if_ddr3_emif_0_mp_cmd_reset_n_0_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset mm_clock_crossing_bridge_0_m0_reset_reset_bridge_in_reset_reset : in std_logic := 'X'; -- reset mm_clock_crossing_bridge_0_m0_address : in std_logic_vector(26 downto 0) := (others => 'X'); -- address mm_clock_crossing_bridge_0_m0_waitrequest : out std_logic; -- waitrequest mm_clock_crossing_bridge_0_m0_burstcount : in std_logic_vector(0 downto 0) := (others => 'X'); -- burstcount mm_clock_crossing_bridge_0_m0_byteenable : in std_logic_vector(3 downto 0) := (others => 'X'); -- byteenable mm_clock_crossing_bridge_0_m0_read : in std_logic := 'X'; -- read mm_clock_crossing_bridge_0_m0_readdata : out std_logic_vector(31 downto 0); -- readdata mm_clock_crossing_bridge_0_m0_readdatavalid : out std_logic; -- readdatavalid mm_clock_crossing_bridge_0_m0_write : in std_logic := 'X'; -- write mm_clock_crossing_bridge_0_m0_writedata : in std_logic_vector(31 downto 0) := (others => 'X'); -- writedata mm_clock_crossing_bridge_0_m0_debugaccess : in std_logic := 'X'; -- debugaccess mem_if_ddr3_emif_0_avl_0_address : out std_logic_vector(26 downto 0); -- address mem_if_ddr3_emif_0_avl_0_write : out std_logic; -- write mem_if_ddr3_emif_0_avl_0_read : out std_logic; -- read mem_if_ddr3_emif_0_avl_0_readdata : in std_logic_vector(31 downto 0) := (others => 'X'); -- readdata mem_if_ddr3_emif_0_avl_0_writedata : out std_logic_vector(31 downto 0); -- writedata mem_if_ddr3_emif_0_avl_0_beginbursttransfer : out std_logic; -- beginbursttransfer mem_if_ddr3_emif_0_avl_0_burstcount : out std_logic_vector(2 downto 0); -- burstcount mem_if_ddr3_emif_0_avl_0_byteenable : out std_logic_vector(3 downto 0); -- byteenable mem_if_ddr3_emif_0_avl_0_readdatavalid : in std_logic := 'X'; -- readdatavalid mem_if_ddr3_emif_0_avl_0_waitrequest : in std_logic := 'X' -- waitrequest ); end component ddr3_mm_interconnect_0; component altera_reset_controller is generic ( NUM_RESET_INPUTS : integer := 6; OUTPUT_RESET_SYNC_EDGES : string := "deassert"; SYNC_DEPTH : integer := 2; RESET_REQUEST_PRESENT : integer := 0; RESET_REQ_WAIT_TIME : integer := 1; MIN_RST_ASSERTION_TIME : integer := 3; RESET_REQ_EARLY_DSRT_TIME : integer := 1; USE_RESET_REQUEST_IN0 : integer := 0; USE_RESET_REQUEST_IN1 : integer := 0; USE_RESET_REQUEST_IN2 : integer := 0; USE_RESET_REQUEST_IN3 : integer := 0; USE_RESET_REQUEST_IN4 : integer := 0; USE_RESET_REQUEST_IN5 : integer := 0; USE_RESET_REQUEST_IN6 : integer := 0; USE_RESET_REQUEST_IN7 : integer := 0; USE_RESET_REQUEST_IN8 : integer := 0; USE_RESET_REQUEST_IN9 : integer := 0; USE_RESET_REQUEST_IN10 : integer := 0; USE_RESET_REQUEST_IN11 : integer := 0; USE_RESET_REQUEST_IN12 : integer := 0; USE_RESET_REQUEST_IN13 : integer := 0; USE_RESET_REQUEST_IN14 : integer := 0; USE_RESET_REQUEST_IN15 : integer := 0; ADAPT_RESET_REQUEST : integer := 0 ); port ( reset_in0 : in std_logic := 'X'; -- reset clk : in std_logic := 'X'; -- clk reset_out : out std_logic; -- reset reset_req : out std_logic; -- reset_req reset_req_in0 : in std_logic := 'X'; -- reset_req reset_in1 : in std_logic := 'X'; -- reset reset_req_in1 : in std_logic := 'X'; -- reset_req reset_in2 : in std_logic := 'X'; -- reset reset_req_in2 : in std_logic := 'X'; -- reset_req reset_in3 : in std_logic := 'X'; -- reset reset_req_in3 : in std_logic := 'X'; -- reset_req reset_in4 : in std_logic := 'X'; -- reset reset_req_in4 : in std_logic := 'X'; -- reset_req reset_in5 : in std_logic := 'X'; -- reset reset_req_in5 : in std_logic := 'X'; -- reset_req reset_in6 : in std_logic := 'X'; -- reset reset_req_in6 : in std_logic := 'X'; -- reset_req reset_in7 : in std_logic := 'X'; -- reset reset_req_in7 : in std_logic := 'X'; -- reset_req reset_in8 : in std_logic := 'X'; -- reset reset_req_in8 : in std_logic := 'X'; -- reset_req reset_in9 : in std_logic := 'X'; -- reset reset_req_in9 : in std_logic := 'X'; -- reset_req reset_in10 : in std_logic := 'X'; -- reset reset_req_in10 : in std_logic := 'X'; -- reset_req reset_in11 : in std_logic := 'X'; -- reset reset_req_in11 : in std_logic := 'X'; -- reset_req reset_in12 : in std_logic := 'X'; -- reset reset_req_in12 : in std_logic := 'X'; -- reset_req reset_in13 : in std_logic := 'X'; -- reset reset_req_in13 : in std_logic := 'X'; -- reset_req reset_in14 : in std_logic := 'X'; -- reset reset_req_in14 : in std_logic := 'X'; -- reset_req reset_in15 : in std_logic := 'X'; -- reset reset_req_in15 : in std_logic := 'X' -- reset_req ); end component altera_reset_controller; signal mem_if_ddr3_emif_0_afi_half_clk_clk : std_logic; -- mem_if_ddr3_emif_0:afi_half_clk -> [refresh_clk_clk, mem_if_ddr3_emif_0:mp_cmd_clk_0_clk, mem_if_ddr3_emif_0:mp_rfifo_clk_0_clk, mem_if_ddr3_emif_0:mp_wfifo_clk_0_clk, mm_clock_crossing_bridge_0:m0_clk, mm_interconnect_0:clk_1_clk_clk, mm_interconnect_0:mem_if_ddr3_emif_0_afi_half_clk_clk, rst_controller:clk] signal mem_if_ddr3_emif_0_afi_reset_export_reset : std_logic; -- mem_if_ddr3_emif_0:afi_reset_export_n -> mem_if_ddr3_emif_0_afi_reset_export_reset:in signal mm_clock_crossing_bridge_0_m0_waitrequest : std_logic; -- mm_interconnect_0:mm_clock_crossing_bridge_0_m0_waitrequest -> mm_clock_crossing_bridge_0:m0_waitrequest signal mm_clock_crossing_bridge_0_m0_readdata : std_logic_vector(31 downto 0); -- mm_interconnect_0:mm_clock_crossing_bridge_0_m0_readdata -> mm_clock_crossing_bridge_0:m0_readdata signal mm_clock_crossing_bridge_0_m0_debugaccess : std_logic; -- mm_clock_crossing_bridge_0:m0_debugaccess -> mm_interconnect_0:mm_clock_crossing_bridge_0_m0_debugaccess signal mm_clock_crossing_bridge_0_m0_address : std_logic_vector(26 downto 0); -- mm_clock_crossing_bridge_0:m0_address -> mm_interconnect_0:mm_clock_crossing_bridge_0_m0_address signal mm_clock_crossing_bridge_0_m0_read : std_logic; -- mm_clock_crossing_bridge_0:m0_read -> mm_interconnect_0:mm_clock_crossing_bridge_0_m0_read signal mm_clock_crossing_bridge_0_m0_byteenable : std_logic_vector(3 downto 0); -- mm_clock_crossing_bridge_0:m0_byteenable -> mm_interconnect_0:mm_clock_crossing_bridge_0_m0_byteenable signal mm_clock_crossing_bridge_0_m0_readdatavalid : std_logic; -- mm_interconnect_0:mm_clock_crossing_bridge_0_m0_readdatavalid -> mm_clock_crossing_bridge_0:m0_readdatavalid signal mm_clock_crossing_bridge_0_m0_writedata : std_logic_vector(31 downto 0); -- mm_clock_crossing_bridge_0:m0_writedata -> mm_interconnect_0:mm_clock_crossing_bridge_0_m0_writedata signal mm_clock_crossing_bridge_0_m0_write : std_logic; -- mm_clock_crossing_bridge_0:m0_write -> mm_interconnect_0:mm_clock_crossing_bridge_0_m0_write signal mm_clock_crossing_bridge_0_m0_burstcount : std_logic_vector(0 downto 0); -- mm_clock_crossing_bridge_0:m0_burstcount -> mm_interconnect_0:mm_clock_crossing_bridge_0_m0_burstcount signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_beginbursttransfer : std_logic; -- mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_beginbursttransfer -> mem_if_ddr3_emif_0:avl_burstbegin_0 signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_readdata : std_logic_vector(31 downto 0); -- mem_if_ddr3_emif_0:avl_rdata_0 -> mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_readdata signal mem_if_ddr3_emif_0_avl_0_waitrequest : std_logic; -- mem_if_ddr3_emif_0:avl_ready_0 -> mem_if_ddr3_emif_0_avl_0_waitrequest:in signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_address : std_logic_vector(26 downto 0); -- mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_address -> mem_if_ddr3_emif_0:avl_addr_0 signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_read : std_logic; -- mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_read -> mem_if_ddr3_emif_0:avl_read_req_0 signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_byteenable : std_logic_vector(3 downto 0); -- mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_byteenable -> mem_if_ddr3_emif_0:avl_be_0 signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_readdatavalid : std_logic; -- mem_if_ddr3_emif_0:avl_rdata_valid_0 -> mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_readdatavalid signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_write : std_logic; -- mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_write -> mem_if_ddr3_emif_0:avl_write_req_0 signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_writedata : std_logic_vector(31 downto 0); -- mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_writedata -> mem_if_ddr3_emif_0:avl_wdata_0 signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_burstcount : std_logic_vector(2 downto 0); -- mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_burstcount -> mem_if_ddr3_emif_0:avl_size_0 signal rst_controller_reset_out_reset : std_logic; -- rst_controller:reset_out -> [mm_clock_crossing_bridge_0:m0_reset, mm_interconnect_0:mm_clock_crossing_bridge_0_m0_reset_reset_bridge_in_reset_reset] signal rst_controller_001_reset_out_reset : std_logic; -- rst_controller_001:reset_out -> mm_clock_crossing_bridge_0:s0_reset signal reset_n_reset_n_ports_inv : std_logic; -- reset_n_reset_n:inv -> rst_controller_001:reset_in0 signal softreset_n_reset_n_ports_inv : std_logic; -- softreset_n_reset_n:inv -> [mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_0:mem_if_ddr3_emif_0_mp_cmd_reset_n_0_reset_bridge_in_reset_reset] signal mem_if_ddr3_emif_0_afi_reset_export_reset_ports_inv : std_logic; -- mem_if_ddr3_emif_0_afi_reset_export_reset:inv -> rst_controller:reset_in0 signal mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_inv : std_logic; -- mem_if_ddr3_emif_0_avl_0_waitrequest:inv -> mm_interconnect_0:mem_if_ddr3_emif_0_avl_0_waitrequest begin mem_if_ddr3_emif_0 : component ddr3_mem_if_ddr3_emif_0 port map ( pll_ref_clk => ddrrefclk_clk, -- pll_ref_clk.clk global_reset_n => reset_n_reset_n, -- global_reset.reset_n soft_reset_n => softreset_n_reset_n, -- soft_reset.reset_n afi_clk => open, -- afi_clk.clk afi_half_clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- afi_half_clk.clk afi_reset_n => open, -- afi_reset.reset_n afi_reset_export_n => mem_if_ddr3_emif_0_afi_reset_export_reset, -- afi_reset_export.reset_n mem_a => ddrext_mem_a, -- memory.mem_a mem_ba => ddrext_mem_ba, -- .mem_ba mem_ck => ddrext_mem_ck, -- .mem_ck mem_ck_n => ddrext_mem_ck_n, -- .mem_ck_n mem_cke => ddrext_mem_cke, -- .mem_cke mem_cs_n => ddrext_mem_cs_n, -- .mem_cs_n mem_dm => ddrext_mem_dm, -- .mem_dm mem_ras_n => ddrext_mem_ras_n, -- .mem_ras_n mem_cas_n => ddrext_mem_cas_n, -- .mem_cas_n mem_we_n => ddrext_mem_we_n, -- .mem_we_n mem_reset_n => ddrext_mem_reset_n, -- .mem_reset_n mem_dq => ddrext_mem_dq, -- .mem_dq mem_dqs => ddrext_mem_dqs, -- .mem_dqs mem_dqs_n => ddrext_mem_dqs_n, -- .mem_dqs_n mem_odt => ddrext_mem_odt, -- .mem_odt avl_ready_0 => mem_if_ddr3_emif_0_avl_0_waitrequest, -- avl_0.waitrequest_n avl_burstbegin_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_beginbursttransfer, -- .beginbursttransfer avl_addr_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_address, -- .address avl_rdata_valid_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_readdatavalid, -- .readdatavalid avl_rdata_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_readdata, -- .readdata avl_wdata_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_writedata, -- .writedata avl_be_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_byteenable, -- .byteenable avl_read_req_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_read, -- .read avl_write_req_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_write, -- .write avl_size_0 => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_burstcount, -- .burstcount mp_cmd_clk_0_clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- mp_cmd_clk_0.clk mp_cmd_reset_n_0_reset_n => softreset_n_reset_n, -- mp_cmd_reset_n_0.reset_n mp_rfifo_clk_0_clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- mp_rfifo_clk_0.clk mp_rfifo_reset_n_0_reset_n => softreset_n_reset_n, -- mp_rfifo_reset_n_0.reset_n mp_wfifo_clk_0_clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- mp_wfifo_clk_0.clk mp_wfifo_reset_n_0_reset_n => softreset_n_reset_n, -- mp_wfifo_reset_n_0.reset_n local_init_done => ddrstatus_local_init_done, -- status.local_init_done local_cal_success => ddrstatus_local_cal_success, -- .local_cal_success local_cal_fail => ddrstatus_local_cal_fail, -- .local_cal_fail local_refresh_req => ddrrefresh_local_refresh_req, -- user_refresh.local_refresh_req local_refresh_chip => ddrrefresh_local_refresh_chip, -- .local_refresh_chip local_refresh_ack => ddrrefresh_local_refresh_ack, -- .local_refresh_ack oct_rzqin => ddroct_rzqin, -- oct.rzqin pll_mem_clk => ddrpll_pll_mem_clk, -- pll_sharing.pll_mem_clk pll_write_clk => ddrpll_pll_write_clk, -- .pll_write_clk pll_locked => ddrpll_pll_locked, -- .pll_locked pll_write_clk_pre_phy_clk => ddrpll_pll_write_clk_pre_phy_clk, -- .pll_write_clk_pre_phy_clk pll_addr_cmd_clk => ddrpll_pll_addr_cmd_clk, -- .pll_addr_cmd_clk pll_avl_clk => ddrpll_pll_avl_clk, -- .pll_avl_clk pll_config_clk => ddrpll_pll_config_clk, -- .pll_config_clk pll_mem_phy_clk => ddrpll_pll_mem_phy_clk, -- .pll_mem_phy_clk afi_phy_clk => ddrpll_afi_phy_clk, -- .afi_phy_clk pll_avl_phy_clk => ddrpll_pll_avl_phy_clk -- .pll_avl_phy_clk ); mm_clock_crossing_bridge_0 : component altera_avalon_mm_clock_crossing_bridge generic map ( DATA_WIDTH => 32, SYMBOL_WIDTH => 8, HDL_ADDR_WIDTH => 27, BURSTCOUNT_WIDTH => 1, COMMAND_FIFO_DEPTH => 4, RESPONSE_FIFO_DEPTH => 4, MASTER_SYNC_DEPTH => 2, SLAVE_SYNC_DEPTH => 2 ) port map ( m0_clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- m0_clk.clk m0_reset => rst_controller_reset_out_reset, -- m0_reset.reset s0_clk => clkatari_clk, -- s0_clk.clk s0_reset => rst_controller_001_reset_out_reset, -- s0_reset.reset s0_waitrequest => ddrint_waitrequest, -- s0.waitrequest s0_readdata => ddrint_readdata, -- .readdata s0_readdatavalid => ddrint_readdatavalid, -- .readdatavalid s0_burstcount => ddrint_burstcount, -- .burstcount s0_writedata => ddrint_writedata, -- .writedata s0_address => ddrint_address, -- .address s0_write => ddrint_write, -- .write s0_read => ddrint_read, -- .read s0_byteenable => ddrint_byteenable, -- .byteenable s0_debugaccess => ddrint_debugaccess, -- .debugaccess m0_waitrequest => mm_clock_crossing_bridge_0_m0_waitrequest, -- m0.waitrequest m0_readdata => mm_clock_crossing_bridge_0_m0_readdata, -- .readdata m0_readdatavalid => mm_clock_crossing_bridge_0_m0_readdatavalid, -- .readdatavalid m0_burstcount => mm_clock_crossing_bridge_0_m0_burstcount, -- .burstcount m0_writedata => mm_clock_crossing_bridge_0_m0_writedata, -- .writedata m0_address => mm_clock_crossing_bridge_0_m0_address, -- .address m0_write => mm_clock_crossing_bridge_0_m0_write, -- .write m0_read => mm_clock_crossing_bridge_0_m0_read, -- .read m0_byteenable => mm_clock_crossing_bridge_0_m0_byteenable, -- .byteenable m0_debugaccess => mm_clock_crossing_bridge_0_m0_debugaccess -- .debugaccess ); mm_interconnect_0 : component ddr3_mm_interconnect_0 port map ( clk_1_clk_clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- clk_1_clk.clk mem_if_ddr3_emif_0_afi_half_clk_clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- mem_if_ddr3_emif_0_afi_half_clk.clk mem_if_ddr3_emif_0_avl_0_translator_reset_reset_bridge_in_reset_reset => softreset_n_reset_n_ports_inv, -- mem_if_ddr3_emif_0_avl_0_translator_reset_reset_bridge_in_reset.reset mem_if_ddr3_emif_0_mp_cmd_reset_n_0_reset_bridge_in_reset_reset => softreset_n_reset_n_ports_inv, -- mem_if_ddr3_emif_0_mp_cmd_reset_n_0_reset_bridge_in_reset.reset mm_clock_crossing_bridge_0_m0_reset_reset_bridge_in_reset_reset => rst_controller_reset_out_reset, -- mm_clock_crossing_bridge_0_m0_reset_reset_bridge_in_reset.reset mm_clock_crossing_bridge_0_m0_address => mm_clock_crossing_bridge_0_m0_address, -- mm_clock_crossing_bridge_0_m0.address mm_clock_crossing_bridge_0_m0_waitrequest => mm_clock_crossing_bridge_0_m0_waitrequest, -- .waitrequest mm_clock_crossing_bridge_0_m0_burstcount => mm_clock_crossing_bridge_0_m0_burstcount, -- .burstcount mm_clock_crossing_bridge_0_m0_byteenable => mm_clock_crossing_bridge_0_m0_byteenable, -- .byteenable mm_clock_crossing_bridge_0_m0_read => mm_clock_crossing_bridge_0_m0_read, -- .read mm_clock_crossing_bridge_0_m0_readdata => mm_clock_crossing_bridge_0_m0_readdata, -- .readdata mm_clock_crossing_bridge_0_m0_readdatavalid => mm_clock_crossing_bridge_0_m0_readdatavalid, -- .readdatavalid mm_clock_crossing_bridge_0_m0_write => mm_clock_crossing_bridge_0_m0_write, -- .write mm_clock_crossing_bridge_0_m0_writedata => mm_clock_crossing_bridge_0_m0_writedata, -- .writedata mm_clock_crossing_bridge_0_m0_debugaccess => mm_clock_crossing_bridge_0_m0_debugaccess, -- .debugaccess mem_if_ddr3_emif_0_avl_0_address => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_address, -- mem_if_ddr3_emif_0_avl_0.address mem_if_ddr3_emif_0_avl_0_write => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_write, -- .write mem_if_ddr3_emif_0_avl_0_read => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_read, -- .read mem_if_ddr3_emif_0_avl_0_readdata => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_readdata, -- .readdata mem_if_ddr3_emif_0_avl_0_writedata => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_writedata, -- .writedata mem_if_ddr3_emif_0_avl_0_beginbursttransfer => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_beginbursttransfer, -- .beginbursttransfer mem_if_ddr3_emif_0_avl_0_burstcount => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_burstcount, -- .burstcount mem_if_ddr3_emif_0_avl_0_byteenable => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_byteenable, -- .byteenable mem_if_ddr3_emif_0_avl_0_readdatavalid => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_readdatavalid, -- .readdatavalid mem_if_ddr3_emif_0_avl_0_waitrequest => mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_inv -- .waitrequest ); rst_controller : component altera_reset_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => mem_if_ddr3_emif_0_afi_reset_export_reset_ports_inv, -- reset_in0.reset clk => mem_if_ddr3_emif_0_afi_half_clk_clk, -- clk.clk reset_out => rst_controller_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); rst_controller_001 : component altera_reset_controller generic map ( NUM_RESET_INPUTS => 1, OUTPUT_RESET_SYNC_EDGES => "deassert", SYNC_DEPTH => 2, RESET_REQUEST_PRESENT => 0, RESET_REQ_WAIT_TIME => 1, MIN_RST_ASSERTION_TIME => 3, RESET_REQ_EARLY_DSRT_TIME => 1, USE_RESET_REQUEST_IN0 => 0, USE_RESET_REQUEST_IN1 => 0, USE_RESET_REQUEST_IN2 => 0, USE_RESET_REQUEST_IN3 => 0, USE_RESET_REQUEST_IN4 => 0, USE_RESET_REQUEST_IN5 => 0, USE_RESET_REQUEST_IN6 => 0, USE_RESET_REQUEST_IN7 => 0, USE_RESET_REQUEST_IN8 => 0, USE_RESET_REQUEST_IN9 => 0, USE_RESET_REQUEST_IN10 => 0, USE_RESET_REQUEST_IN11 => 0, USE_RESET_REQUEST_IN12 => 0, USE_RESET_REQUEST_IN13 => 0, USE_RESET_REQUEST_IN14 => 0, USE_RESET_REQUEST_IN15 => 0, ADAPT_RESET_REQUEST => 0 ) port map ( reset_in0 => reset_n_reset_n_ports_inv, -- reset_in0.reset clk => clkatari_clk, -- clk.clk reset_out => rst_controller_001_reset_out_reset, -- reset_out.reset reset_req => open, -- (terminated) reset_req_in0 => '0', -- (terminated) reset_in1 => '0', -- (terminated) reset_req_in1 => '0', -- (terminated) reset_in2 => '0', -- (terminated) reset_req_in2 => '0', -- (terminated) reset_in3 => '0', -- (terminated) reset_req_in3 => '0', -- (terminated) reset_in4 => '0', -- (terminated) reset_req_in4 => '0', -- (terminated) reset_in5 => '0', -- (terminated) reset_req_in5 => '0', -- (terminated) reset_in6 => '0', -- (terminated) reset_req_in6 => '0', -- (terminated) reset_in7 => '0', -- (terminated) reset_req_in7 => '0', -- (terminated) reset_in8 => '0', -- (terminated) reset_req_in8 => '0', -- (terminated) reset_in9 => '0', -- (terminated) reset_req_in9 => '0', -- (terminated) reset_in10 => '0', -- (terminated) reset_req_in10 => '0', -- (terminated) reset_in11 => '0', -- (terminated) reset_req_in11 => '0', -- (terminated) reset_in12 => '0', -- (terminated) reset_req_in12 => '0', -- (terminated) reset_in13 => '0', -- (terminated) reset_req_in13 => '0', -- (terminated) reset_in14 => '0', -- (terminated) reset_req_in14 => '0', -- (terminated) reset_in15 => '0', -- (terminated) reset_req_in15 => '0' -- (terminated) ); reset_n_reset_n_ports_inv <= not reset_n_reset_n; softreset_n_reset_n_ports_inv <= not softreset_n_reset_n; mem_if_ddr3_emif_0_afi_reset_export_reset_ports_inv <= not mem_if_ddr3_emif_0_afi_reset_export_reset; mm_interconnect_0_mem_if_ddr3_emif_0_avl_0_inv <= not mem_if_ddr3_emif_0_avl_0_waitrequest; refresh_clk_clk <= mem_if_ddr3_emif_0_afi_half_clk_clk; end architecture rtl; -- of ddr3