Info: Starting: Create block symbol file (.bsf)
Info: qsys-generate /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3.qsys --block-symbol-file --output-directory=/home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3 --family="Cyclone V" --part=5CEFA5F23C8
Progress: Loading vampire_atari/ddr3.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 23.1]
Progress: Parameterizing module clk_0
Progress: Adding clk_1 [clock_source 23.1]
Progress: Parameterizing module clk_1
Progress: Adding clock_bridge_0 [altera_clock_bridge 23.1]
Progress: Parameterizing module clock_bridge_0
Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 23.1]
Progress: Parameterizing module mem_if_ddr3_emif_0
Progress: Adding mm_clock_crossing_bridge_0 [altera_avalon_mm_clock_crossing_bridge 23.1]
Progress: Parameterizing module mm_clock_crossing_bridge_0
Progress: Adding reset_bridge_0 [altera_reset_bridge 23.1]
Progress: Parameterizing module reset_bridge_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: ddr3.mem_if_ddr3_emif_0: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Warning: ddr3.mem_if_ddr3_emif_0.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
Info: qsys-generate succeeded.
Info: Finished: Create block symbol file (.bsf)
Info: 
Info: Starting: Create HDL design files for synthesis
Info: qsys-generate /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3.qsys --synthesis=VHDL --output-directory=/home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis --family="Cyclone V" --part=5CEFA5F23C8
Progress: Loading vampire_atari/ddr3.qsys
Progress: Reading input file
Progress: Adding clk_0 [clock_source 23.1]
Progress: Parameterizing module clk_0
Progress: Adding clk_1 [clock_source 23.1]
Progress: Parameterizing module clk_1
Progress: Adding clock_bridge_0 [altera_clock_bridge 23.1]
Progress: Parameterizing module clock_bridge_0
Progress: Adding mem_if_ddr3_emif_0 [altera_mem_if_ddr3_emif 23.1]
Progress: Parameterizing module mem_if_ddr3_emif_0
Progress: Adding mm_clock_crossing_bridge_0 [altera_avalon_mm_clock_crossing_bridge 23.1]
Progress: Parameterizing module mm_clock_crossing_bridge_0
Progress: Adding reset_bridge_0 [altera_reset_bridge 23.1]
Progress: Parameterizing module reset_bridge_0
Progress: Building connections
Progress: Parameterizing connections
Progress: Validating
Progress: Done reading input file
Warning: ddr3.mem_if_ddr3_emif_0: 'Quick' simulation modes are NOT timing accurate. Some simulation memory models may issue warnings or errors
Warning: ddr3.mem_if_ddr3_emif_0.pll_bridge: pll_bridge.pll_sharing cannot be both connected and exported
Info: ddr3: Generating ddr3 "ddr3" for QUARTUS_SYNTH
Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave mem_if_ddr3_emif_0.avl_0 because the master has burstcount signal 1 bit wide, but the slave is 3 bit wide.
Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave mem_if_ddr3_emif_0.avl_0 because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide.
Info: Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave mem_if_ddr3_emif_0.avl_0 because they have different clock source.
Info: Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0
Info: Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0
Info: mem_if_ddr3_emif_0: "ddr3" instantiated altera_mem_if_ddr3_emif "mem_if_ddr3_emif_0"
Info: mm_clock_crossing_bridge_0: "ddr3" instantiated altera_avalon_mm_clock_crossing_bridge "mm_clock_crossing_bridge_0"
Info: avalon_st_adapter: Inserting error_adapter: error_adapter_0
Info: mm_interconnect_0: "ddr3" instantiated altera_mm_interconnect "mm_interconnect_0"
Info: rst_controller: "ddr3" instantiated altera_reset_controller "rst_controller"
Info: pll0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_pll "pll0"
Info: p0: Generating clock pair generator
Info: p0: Generating ddr3_mem_if_ddr3_emif_0_p0_altdqdqs
Info: p0: 
Info: p0: *****************************
Info: p0: 
Info: p0: Remember to run the ddr3_mem_if_ddr3_emif_0_p0_pin_assignments.tcl
Info: p0: script after running Synthesis and before Fitting.
Info: p0: 
Info: p0: *****************************
Info: p0: 
Info: p0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_hard_phy_core "p0"
Info: s0: Generating Qsys sequencer system
Info: s0: QSYS sequencer system generated successfully
Info: s0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_qseq "s0"
Info: c0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_hard_memory_controller "c0"
Info: oct0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_oct "oct0"
Info: dll0: "mem_if_ddr3_emif_0" instantiated altera_mem_if_dll "dll0"
Info: mm_clock_crossing_bridge_0_m0_translator: "mm_interconnect_0" instantiated altera_merlin_master_translator "mm_clock_crossing_bridge_0_m0_translator"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_translator.sv
Info: mem_if_ddr3_emif_0_avl_0_translator: "mm_interconnect_0" instantiated altera_merlin_slave_translator "mem_if_ddr3_emif_0_avl_0_translator"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_translator.sv
Info: mm_clock_crossing_bridge_0_m0_agent: "mm_interconnect_0" instantiated altera_merlin_master_agent "mm_clock_crossing_bridge_0_m0_agent"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_agent.sv
Info: mem_if_ddr3_emif_0_avl_0_agent: "mm_interconnect_0" instantiated altera_merlin_slave_agent "mem_if_ddr3_emif_0_avl_0_agent"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_agent.sv
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_burst_uncompressor.sv
Info: mem_if_ddr3_emif_0_avl_0_agent_rsp_fifo: "mm_interconnect_0" instantiated altera_avalon_sc_fifo "mem_if_ddr3_emif_0_avl_0_agent_rsp_fifo"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_avalon_sc_fifo.v
Info: router: "mm_interconnect_0" instantiated altera_merlin_router "router"
Info: router_001: "mm_interconnect_0" instantiated altera_merlin_router "router_001"
Info: cmd_demux: "mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"
Info: cmd_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv
Info: rsp_mux: "mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv
Info: crosser: "mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"
Info: Reusing file /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_std_synchronizer_nocut.v
Info: avalon_st_adapter: "mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"
Info: error_adapter_0: "avalon_st_adapter" instantiated error_adapter "error_adapter_0"
Info: ddr3: Done "ddr3" with 24 modules, 91 files
Info: qsys-generate succeeded.
Info: Finished: Create HDL design files for synthesis