queue size: 0 starting:ddr3 "ddr3" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 6 modules, 17 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave mem_if_ddr3_emif_0.avl_0 because the master has burstcount signal 1 bit wide, but the slave is 3 bit wide. Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave mem_if_ddr3_emif_0.avl_0 because the master has debugaccess signal 1 bit wide, but the slave is 0 bit wide. Interconnect is inserted between master mm_clock_crossing_bridge_0.m0 and slave mem_if_ddr3_emif_0.avl_0 because they have different clock source. 4 modules, 5 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform 6 modules, 11 connections]]> Transform: IDPadTransform Transform: DomainTransform Transform merlin_domain_transform not run on matched interfaces mm_clock_crossing_bridge_0.m0 and mm_clock_crossing_bridge_0_m0_translator.avalon_anti_master_0 Transform merlin_domain_transform not run on matched interfaces mem_if_ddr3_emif_0_avl_0_translator.avalon_anti_slave_0 and mem_if_ddr3_emif_0.avl_0 11 modules, 32 connections]]> Transform: RouterTransform 13 modules, 38 connections]]> Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform 16 modules, 44 connections]]> Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Inserting clock-crossing logic between cmd_demux.src0 and cmd_mux.sink0 Inserting clock-crossing logic between rsp_demux.src0 and rsp_mux.sink0 18 modules, 54 connections]]> Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform 23 modules, 77 connections]]> Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 7 modules, 23 connections]]> 7 modules, 23 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation 9 modules, 27 connections]]> ddr3" reuses altera_mem_if_ddr3_emif "submodules/ddr3_mem_if_ddr3_emif_0"]]> ddr3" reuses altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge"]]> ddr3" reuses altera_mm_interconnect "submodules/ddr3_mm_interconnect_0"]]> ddr3" reuses altera_reset_controller "submodules/altera_reset_controller"]]> ddr3" reuses altera_reset_controller "submodules/altera_reset_controller"]]> queue size: 4 starting:altera_mem_if_ddr3_emif "submodules/ddr3_mem_if_ddr3_emif_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 17 modules, 34 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 17 modules, 34 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation mem_if_ddr3_emif_0" reuses altera_mem_if_ddr3_pll "submodules/ddr3_mem_if_ddr3_emif_0_pll0"]]> mem_if_ddr3_emif_0" reuses altera_mem_if_ddr3_hard_phy_core "submodules/ddr3_mem_if_ddr3_emif_0_p0"]]> mem_if_ddr3_emif_0" reuses altera_mem_if_ddr3_qseq "submodules/ddr3_mem_if_ddr3_emif_0_s0"]]> mem_if_ddr3_emif_0" reuses altera_mem_if_ddr3_hard_memory_controller "submodules/altera_mem_if_hard_memory_controller_top_cyclonev"]]> mem_if_ddr3_emif_0" reuses altera_mem_if_oct "submodules/altera_mem_if_oct_cyclonev"]]> mem_if_ddr3_emif_0" reuses altera_mem_if_dll "submodules/altera_mem_if_dll_cyclonev"]]> ddr3" instantiated altera_mem_if_ddr3_emif "mem_if_ddr3_emif_0"]]> queue size: 20 starting:altera_mem_if_ddr3_pll "submodules/ddr3_mem_if_ddr3_emif_0_pll0" mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_pll "pll0"]]> queue size: 19 starting:altera_mem_if_ddr3_hard_phy_core "submodules/ddr3_mem_if_ddr3_emif_0_p0" Generating clock pair generator Generating ddr3_mem_if_ddr3_emif_0_p0_altdqdqs ***************************** Remember to run the ddr3_mem_if_ddr3_emif_0_p0_pin_assignments.tcl script after running Synthesis and before Fitting. ***************************** mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_hard_phy_core "p0"]]> queue size: 18 starting:altera_mem_if_ddr3_qseq "submodules/ddr3_mem_if_ddr3_emif_0_s0" Generating Qsys sequencer system QSYS sequencer system generated successfully mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_qseq "s0"]]> queue size: 17 starting:altera_mem_if_ddr3_hard_memory_controller "submodules/altera_mem_if_hard_memory_controller_top_cyclonev" mem_if_ddr3_emif_0" instantiated altera_mem_if_ddr3_hard_memory_controller "c0"]]> queue size: 16 starting:altera_mem_if_oct "submodules/altera_mem_if_oct_cyclonev" mem_if_ddr3_emif_0" instantiated altera_mem_if_oct "oct0"]]> queue size: 15 starting:altera_mem_if_dll "submodules/altera_mem_if_dll_cyclonev" mem_if_ddr3_emif_0" instantiated altera_mem_if_dll "dll0"]]> queue size: 9 starting:altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" ddr3" instantiated altera_avalon_mm_clock_crossing_bridge "mm_clock_crossing_bridge_0"]]> queue size: 8 starting:altera_mm_interconnect "submodules/ddr3_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 19 modules, 51 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 19 modules, 51 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 19 modules, 51 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.002s Timing: COM:3/0.011s/0.014s 20 modules, 54 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/ddr3_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/ddr3_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/ddr3_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/ddr3_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter"]]> ddr3" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 14 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "mm_clock_crossing_bridge_0_m0_translator"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 13 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "mem_if_ddr3_emif_0_avl_0_translator"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 12 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "mm_clock_crossing_bridge_0_m0_agent"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_agent.sv]]> queue size: 11 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "mem_if_ddr3_emif_0_avl_0_agent"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_agent.sv]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 10 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "mem_if_ddr3_emif_0_avl_0_agent_rsp_fifo"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 8 starting:altera_merlin_router "submodules/ddr3_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 7 starting:altera_merlin_router "submodules/ddr3_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 6 starting:altera_merlin_demultiplexer "submodules/ddr3_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 2 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_std_synchronizer_nocut.v]]> queue size: 0 starting:altera_avalon_st_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 22 starting:altera_reset_controller "submodules/altera_reset_controller" ddr3" instantiated altera_reset_controller "rst_controller"]]> queue size: 9 starting:altera_avalon_mm_clock_crossing_bridge "submodules/altera_avalon_mm_clock_crossing_bridge" ddr3" instantiated altera_avalon_mm_clock_crossing_bridge "mm_clock_crossing_bridge_0"]]> queue size: 8 starting:altera_mm_interconnect "submodules/ddr3_mm_interconnect_0" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 19 modules, 51 connections]]> Transform: MMTransform Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 19 modules, 51 connections]]> Transform: InitialInterconnectTransform 0 modules, 0 connections]]> Transform: TerminalIdAssignmentUpdateTransform Transform: DefaultSlaveTransform Transform: TranslatorTransform No Avalon connections, skipping transform Transform: IDPadTransform Transform: DomainTransform Transform: RouterTransform Transform: TrafficLimiterTransform Transform: BurstTransform Transform: TreeTransform Transform: NetworkToSwitchTransform Transform: WidthTransform Transform: RouterTableTransform Transform: ThreadIDMappingTableTransform Transform: ClockCrossingTransform Transform: PipelineTransform Transform: SpotPipelineTransform Transform: PerformanceMonitorTransform Transform: TrafficLimiterUpdateTransform Transform: InsertClockAndResetBridgesTransform Transform: InterconnectConnectionsTagger Transform: HierarchyTransform 19 modules, 51 connections]]> Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Inserting error_adapter: error_adapter_0 Timing: ELA:1/0.001s Timing: ELA:2/0.000s/0.001s Timing: ELA:1/0.002s Timing: COM:3/0.011s/0.014s 20 modules, 54 connections]]> Transform: ResetAdaptation mm_interconnect_0" reuses altera_merlin_master_translator "submodules/altera_merlin_master_translator"]]> mm_interconnect_0" reuses altera_merlin_slave_translator "submodules/altera_merlin_slave_translator"]]> mm_interconnect_0" reuses altera_merlin_master_agent "submodules/altera_merlin_master_agent"]]> mm_interconnect_0" reuses altera_merlin_slave_agent "submodules/altera_merlin_slave_agent"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/ddr3_mm_interconnect_0_router"]]> mm_interconnect_0" reuses altera_merlin_router "submodules/ddr3_mm_interconnect_0_router_001"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/ddr3_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_cmd_mux"]]> mm_interconnect_0" reuses altera_merlin_demultiplexer "submodules/ddr3_mm_interconnect_0_cmd_demux"]]> mm_interconnect_0" reuses altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_rsp_mux"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser"]]> mm_interconnect_0" reuses altera_avalon_st_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter"]]> ddr3" instantiated altera_mm_interconnect "mm_interconnect_0"]]> queue size: 14 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "mm_clock_crossing_bridge_0_m0_translator"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 13 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "mem_if_ddr3_emif_0_avl_0_translator"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 12 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "mm_clock_crossing_bridge_0_m0_agent"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_agent.sv]]> queue size: 11 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "mem_if_ddr3_emif_0_avl_0_agent"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_agent.sv]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 10 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "mem_if_ddr3_emif_0_avl_0_agent_rsp_fifo"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 8 starting:altera_merlin_router "submodules/ddr3_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 7 starting:altera_merlin_router "submodules/ddr3_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 6 starting:altera_merlin_demultiplexer "submodules/ddr3_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 2 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_std_synchronizer_nocut.v]]> queue size: 0 starting:altera_avalon_st_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 22 starting:altera_reset_controller "submodules/altera_reset_controller" ddr3" instantiated altera_reset_controller "rst_controller"]]> queue size: 16 starting:altera_mem_if_oct "submodules/altera_mem_if_oct_cyclonev" mem_if_ddr3_emif_0" instantiated altera_mem_if_oct "oct0"]]> queue size: 15 starting:altera_mem_if_dll "submodules/altera_mem_if_dll_cyclonev" mem_if_ddr3_emif_0" instantiated altera_mem_if_dll "dll0"]]> queue size: 14 starting:altera_merlin_master_translator "submodules/altera_merlin_master_translator" mm_interconnect_0" instantiated altera_merlin_master_translator "mm_clock_crossing_bridge_0_m0_translator"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_translator.sv]]> queue size: 13 starting:altera_merlin_slave_translator "submodules/altera_merlin_slave_translator" mm_interconnect_0" instantiated altera_merlin_slave_translator "mem_if_ddr3_emif_0_avl_0_translator"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_translator.sv]]> queue size: 12 starting:altera_merlin_master_agent "submodules/altera_merlin_master_agent" mm_interconnect_0" instantiated altera_merlin_master_agent "mm_clock_crossing_bridge_0_m0_agent"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_master_agent.sv]]> queue size: 11 starting:altera_merlin_slave_agent "submodules/altera_merlin_slave_agent" mm_interconnect_0" instantiated altera_merlin_slave_agent "mem_if_ddr3_emif_0_avl_0_agent"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_slave_agent.sv]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_burst_uncompressor.sv]]> queue size: 10 starting:altera_avalon_sc_fifo "submodules/altera_avalon_sc_fifo" mm_interconnect_0" instantiated altera_avalon_sc_fifo "mem_if_ddr3_emif_0_avl_0_agent_rsp_fifo"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_avalon_sc_fifo.v]]> queue size: 8 starting:altera_merlin_router "submodules/ddr3_mm_interconnect_0_router" mm_interconnect_0" instantiated altera_merlin_router "router"]]> queue size: 7 starting:altera_merlin_router "submodules/ddr3_mm_interconnect_0_router_001" mm_interconnect_0" instantiated altera_merlin_router "router_001"]]> queue size: 6 starting:altera_merlin_demultiplexer "submodules/ddr3_mm_interconnect_0_cmd_demux" mm_interconnect_0" instantiated altera_merlin_demultiplexer "cmd_demux"]]> queue size: 5 starting:altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_cmd_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "cmd_mux"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 3 starting:altera_merlin_multiplexer "submodules/ddr3_mm_interconnect_0_rsp_mux" mm_interconnect_0" instantiated altera_merlin_multiplexer "rsp_mux"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_merlin_arbitrator.sv]]> queue size: 2 starting:altera_avalon_st_handshake_clock_crosser "submodules/altera_avalon_st_handshake_clock_crosser" mm_interconnect_0" instantiated altera_avalon_st_handshake_clock_crosser "crosser"]]> /home/markw/fpga/svn/repo/branches/trunkv37/atari_800xl/vampire_atari/ddr3/synthesis/submodules/altera_std_synchronizer_nocut.v]]> queue size: 0 starting:altera_avalon_st_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter" Transform: CustomInstructionTransform No custom instruction connections, skipping transform 3 modules, 3 connections]]> Transform: MMTransform Transform: InterruptMapperTransform Transform: InterruptSyncTransform Transform: InterruptFanoutTransform Transform: AvalonStreamingTransform Transform: ResetAdaptation avalon_st_adapter" reuses error_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0"]]> mm_interconnect_0" instantiated altera_avalon_st_adapter "avalon_st_adapter"]]> queue size: 0 starting:error_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]> queue size: 0 starting:error_adapter "submodules/ddr3_mm_interconnect_0_avalon_st_adapter_error_adapter_0" avalon_st_adapter" instantiated error_adapter "error_adapter_0"]]>