---

clk_0

clock_source v23.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 0 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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clk_1

clock_source v23.1

Parameters clockFrequency 50000000 clockFrequencyKnown true inputClockFrequency 166666666 resetSynchronousEdges NONE deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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clock_bridge_0

altera_clock_bridge v23.1

Parameters DERIVED_CLOCK_RATE 166666666 EXPLICIT_CLOCK_RATE 0 NUM_CLOCK_OUTPUTS 1 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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mem_if_ddr3_emif_0

altera_mem_if_ddr3_emif v23.1

Parameters AC_ROM_MR0 0001000110001 AC_ROM_MR0_MIRR 0001001001001 AC_ROM_MR0_CALIB AC_ROM_MR0_DLL_RESET 0001100110000 AC_ROM_MR0_DLL_RESET_MIRR 0001011001000 AC_ROM_MR1 0000001000100 AC_ROM_MR1_MIRR 0000000100100 AC_ROM_MR1_CALIB AC_ROM_MR1_OCD_ENABLE AC_ROM_MR2 0001000001000 AC_ROM_MR2_MIRR 0001000010000 AC_ROM_MR3 0000000000000 AC_ROM_MR3_MIRR 0000000000000 USE_NEG_EDGE_AC_TRANSFER_FOR_HPHY true MR0_BL 1 MR0_BT 0 MR0_CAS_LATENCY 3 MR0_DLL 1 MR0_WR 1 MR0_PD 0 MR1_DLL 0 MR1_ODS 0 MR1_RTT 3 MR1_AL 0 MR1_WL 0 MR1_TDQS 0 MR1_QOFF 0 MR1_DQS 0 MR1_RDQS 0 MR2_CWL 1 MR2_ASR 0 MR2_SRT 0 MR2_SRF 0 MR2_RTT_WR 1 MR3_MPR_RF 0 MR3_MPR 0 MR3_MPR_AA 0 MEM_IF_READ_DQS_WIDTH 2 MEM_IF_WRITE_DQS_WIDTH 2 SCC_DATA_WIDTH 1 MEM_IF_ADDR_WIDTH 15 MEM_IF_ADDR_WIDTH_MIN 13 MEM_IF_ROW_ADDR_WIDTH 15 MEM_IF_COL_ADDR_WIDTH 10 MEM_IF_DM_WIDTH 2 MEM_IF_CS_PER_RANK 1 MEM_IF_NUMBER_OF_RANKS 1 MEM_IF_CS_PER_DIMM 1 MEM_IF_CONTROL_WIDTH 1 MEM_BURST_LENGTH 8 MEM_LEVELING false MEM_IF_DQS_WIDTH 2 MEM_IF_CS_WIDTH 1 MEM_IF_CHIP_BITS 1 MEM_IF_BANKADDR_WIDTH 3 MEM_IF_DQ_WIDTH 16 MEM_IF_CK_WIDTH 1 MEM_IF_CLK_EN_WIDTH 1 MEM_IF_CLK_PAIR_COUNT 1 DEVICE_WIDTH 1 MEM_CLK_MAX_NS 1.25 MEM_CLK_MAX_PS 1250.0 MEM_TRC 17 MEM_TRAS 12 MEM_TRCD 5 MEM_TRP 5 MEM_TREFI 2598 MEM_TRFC 87 CFG_TCCD 1 MEM_TWR 5 MEM_TFAW 15 MEM_TRRD 3 MEM_TRTP 3 MEM_DQS_TO_CLK_CAPTURE_DELAY 450 MEM_CLK_TO_DQS_CAPTURE_DELAY 100000 MEM_IF_ODT_WIDTH 1 MEM_WTCL_INT 6 FLY_BY true RDIMM false LRDIMM false RDIMM_INT 0 LRDIMM_INT 0 MEM_IF_LRDIMM_RM 0 MEM_IF_RD_TO_WR_TURNAROUND_OCT 2 MEM_IF_WR_TO_RD_TURNAROUND_OCT 3 CTL_RD_TO_PCH_EXTRA_CLK 0 CTL_RD_TO_RD_EXTRA_CLK 0 CTL_WR_TO_WR_EXTRA_CLK 0 CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK 1 CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK 2 MEM_TYPE DDR3 MEM_MIRROR_ADDRESSING_DEC 0 MEM_ATCL_INT 0 MEM_REGDIMM_ENABLED false MEM_LRDIMM_ENABLED false MEM_VENDOR Micron MEM_FORMAT DISCRETE AC_PARITY false RDIMM_CONFIG 0 LRDIMM_EXTENDED_CONFIG 0x0 DISCRETE_FLY_BY true DEVICE_DEPTH 1 MEM_MIRROR_ADDRESSING 0 MEM_CLK_FREQ_MAX 800.0 MEM_ROW_ADDR_WIDTH 15 MEM_COL_ADDR_WIDTH 10 MEM_DQ_WIDTH 16 MEM_DQ_PER_DQS 8 MEM_BANKADDR_WIDTH 3 MEM_IF_DM_PINS_EN true MEM_IF_DQSN_EN true MEM_NUMBER_OF_DIMMS 1 MEM_NUMBER_OF_RANKS_PER_DIMM 1 MEM_NUMBER_OF_RANKS_PER_DEVICE 1 MEM_RANK_MULTIPLICATION_FACTOR 1 MEM_CK_WIDTH 1 MEM_CS_WIDTH 1 MEM_CLK_EN_WIDTH 1 ALTMEMPHY_COMPATIBLE_MODE false NEXTGEN true MEM_IF_BOARD_BASE_DELAY 10 MEM_IF_SIM_VALID_WINDOW 0 MEM_GUARANTEED_WRITE_INIT false MEM_VERBOSE true PINGPONGPHY_EN false DUPLICATE_AC false REFRESH_BURST_VALIDATION false AP_MODE_EN 0 AP_MODE false MEM_BL OTF MEM_BT Sequential MEM_ASR Manual MEM_SRT Normal MEM_PD DLL off MEM_DRV_STR RZQ/6 MEM_DLL_EN true MEM_RTT_NOM RZQ/6 MEM_RTT_WR RZQ/4 MEM_WTCL 6 MEM_ATCL Disabled MEM_TCL 7 MEM_AUTO_LEVELING_MODE true MEM_USER_LEVELING_MODE Leveling MEM_INIT_EN false MEM_INIT_FILE DAT_DATA_WIDTH 32 TIMING_TIS 185 TIMING_TIH 130 TIMING_TDS 55 TIMING_TDH 55 TIMING_TDQSQ 125 TIMING_TQH 0.38 TIMING_TDQSCK 225 TIMING_TDQSCKDS 450 TIMING_TDQSCKDM 900 TIMING_TDQSCKDL 1200 TIMING_TDQSS 0.25 TIMING_TQSH 0.4 TIMING_TDSH 0.2 TIMING_TDSS 0.2 MEM_TINIT_US 500 MEM_TINIT_CK 166500 MEM_TDQSCK 1 MEM_TMRD_CK 4 MEM_TRAS_NS 35.0 MEM_TRCD_NS 13.75 MEM_TRP_NS 13.75 MEM_TREFI_US 7.8 MEM_TRFC_NS 260.0 CFG_TCCD_NS 2.5 MEM_TWR_NS 15.0 MEM_TWTR 6 MEM_TFAW_NS 45.0 MEM_TRRD_NS 7.5 MEM_TRTP_NS 7.5 RATE Full MEM_CLK_FREQ 333.0 USE_MEM_CLK_FREQ false USE_DQS_TRACKING false FORCE_DQS_TRACKING AUTO USE_HPS_DQS_TRACKING false TRK_PARALLEL_SCC_LOAD false USE_SHADOW_REGS false FORCE_SHADOW_REGS AUTO DQ_DDR 1 ADDR_CMD_DDR 0 AFI_RATE_RATIO 1 DATA_RATE_RATIO 2 ADDR_RATE_RATIO 1 AFI_ADDR_WIDTH 15 AFI_BANKADDR_WIDTH 3 AFI_CONTROL_WIDTH 1 AFI_CS_WIDTH 1 AFI_CLK_EN_WIDTH 1 AFI_DM_WIDTH 4 AFI_DQ_WIDTH 32 AFI_ODT_WIDTH 1 AFI_WRITE_DQS_WIDTH 2 AFI_RLAT_WIDTH 6 AFI_WLAT_WIDTH 6 AFI_RRANK_WIDTH 2 AFI_WRANK_WIDTH 2 AFI_CLK_PAIR_COUNT 1 MRS_MIRROR_PING_PONG_ATSO false SYS_INFO_DEVICE_FAMILY CYCLONEV PARSE_FRIENDLY_DEVICE_FAMILY CYCLONEV DEVICE_FAMILY Cyclone V PRE_V_SERIES_FAMILY false PARSE_FRIENDLY_DEVICE_FAMILY_CACHE_VALID true PARSE_FRIENDLY_DEVICE_FAMILY_PARAM_VALID false PARSE_FRIENDLY_DEVICE_FAMILY_PARAM DEVICE_FAMILY_PARAM SPEED_GRADE 8 IS_ES_DEVICE false DISABLE_CHILD_MESSAGING false HARD_PHY true HARD_EMIF true HHP_HPS false HHP_HPS_VERIFICATION false HHP_HPS_SIMULATION false HPS_PROTOCOL DEFAULT CUT_NEW_FAMILY_TIMING true EXPORT_CSR_PORT false CSR_ADDR_WIDTH 10 CSR_DATA_WIDTH 8 CSR_BE_WIDTH 1 CTL_CS_WIDTH 1 AVL_ADDR_WIDTH 27 AVL_BE_WIDTH 4 AVL_DATA_WIDTH 32 AVL_SYMBOL_WIDTH 8 AVL_NUM_SYMBOLS 4 AVL_SIZE_WIDTH 3 HR_DDIO_OUT_HAS_THREE_REGS false CTL_ECC_CSR_ENABLED false DWIDTH_RATIO 2 CTL_ODT_ENABLED true CTL_OUTPUT_REGD false CTL_ECC_MULTIPLES_40_72 1 CTL_ECC_MULTIPLES_16_24_40_72 1 CTL_REGDIMM_ENABLED false LOW_LATENCY false CONTROLLER_TYPE nextgen_v110 CTL_TBP_NUM 4 CTL_USR_REFRESH 1 CTL_SELF_REFRESH 0 CFG_TYPE 2 CFG_INTERFACE_WIDTH 16 CFG_BURST_LENGTH 8 CFG_ADDR_ORDER 0 CFG_PDN_EXIT_CYCLES 10 CFG_POWER_SAVING_EXIT_CYCLES 5 CFG_MEM_CLK_ENTRY_CYCLES 10 CFG_SELF_RFSH_EXIT_CYCLES 512 CFG_PORT_WIDTH_WRITE_ODT_CHIP 1 CFG_PORT_WIDTH_READ_ODT_CHIP 1 CFG_WRITE_ODT_CHIP 1 CFG_READ_ODT_CHIP 0 LOCAL_CS_WIDTH 0 CFG_CLR_INTR 0 CFG_ENABLE_NO_DM 0 MEM_ADD_LAT 0 CTL_ENABLE_BURST_INTERRUPT_INT false CTL_ENABLE_BURST_TERMINATE_INT false CFG_ERRCMD_FIFO_REG 0 CFG_ECC_DECODER_REG 0 CTL_ENABLE_WDATA_PATH_LATENCY false CFG_STARVE_LIMIT 10 MEM_AUTO_PD_CYCLES 0 AVL_PORT Port 0 AVL_DATA_WIDTH_PORT_0 32 AVL_ADDR_WIDTH_PORT_0 27 PRIORITY_PORT_0 1 WEIGHT_PORT_0 0 CPORT_TYPE_PORT_0 3 AVL_NUM_SYMBOLS_PORT_0 4 LSB_WFIFO_PORT_0 0 MSB_WFIFO_PORT_0 0 LSB_RFIFO_PORT_0 0 MSB_RFIFO_PORT_0 0 AVL_DATA_WIDTH_PORT_1 1 AVL_ADDR_WIDTH_PORT_1 1 PRIORITY_PORT_1 1 WEIGHT_PORT_1 0 CPORT_TYPE_PORT_1 0 AVL_NUM_SYMBOLS_PORT_1 1 LSB_WFIFO_PORT_1 5 MSB_WFIFO_PORT_1 5 LSB_RFIFO_PORT_1 5 MSB_RFIFO_PORT_1 5 AVL_DATA_WIDTH_PORT_2 1 AVL_ADDR_WIDTH_PORT_2 1 PRIORITY_PORT_2 1 WEIGHT_PORT_2 0 CPORT_TYPE_PORT_2 0 AVL_NUM_SYMBOLS_PORT_2 1 LSB_WFIFO_PORT_2 5 MSB_WFIFO_PORT_2 5 LSB_RFIFO_PORT_2 5 MSB_RFIFO_PORT_2 5 AVL_DATA_WIDTH_PORT_3 1 AVL_ADDR_WIDTH_PORT_3 1 PRIORITY_PORT_3 1 WEIGHT_PORT_3 0 CPORT_TYPE_PORT_3 0 AVL_NUM_SYMBOLS_PORT_3 1 LSB_WFIFO_PORT_3 5 MSB_WFIFO_PORT_3 5 LSB_RFIFO_PORT_3 5 MSB_RFIFO_PORT_3 5 AVL_DATA_WIDTH_PORT_4 1 AVL_ADDR_WIDTH_PORT_4 1 PRIORITY_PORT_4 1 WEIGHT_PORT_4 0 CPORT_TYPE_PORT_4 0 AVL_NUM_SYMBOLS_PORT_4 1 LSB_WFIFO_PORT_4 5 MSB_WFIFO_PORT_4 5 LSB_RFIFO_PORT_4 5 MSB_RFIFO_PORT_4 5 AVL_DATA_WIDTH_PORT_5 1 AVL_ADDR_WIDTH_PORT_5 1 PRIORITY_PORT_5 1 WEIGHT_PORT_5 0 CPORT_TYPE_PORT_5 0 AVL_NUM_SYMBOLS_PORT_5 1 LSB_WFIFO_PORT_5 5 MSB_WFIFO_PORT_5 5 LSB_RFIFO_PORT_5 5 MSB_RFIFO_PORT_5 5 ALLOCATED_RFIFO_PORT F0,None,None,None,None,None ALLOCATED_WFIFO_PORT F0,None,None,None,None,None ENUM_ATTR_COUNTER_ONE_RESET DISABLED ENUM_ATTR_COUNTER_ZERO_RESET DISABLED ENUM_ATTR_STATIC_CONFIG_VALID DISABLED ENUM_AUTO_PCH_ENABLE_0 DISABLED ENUM_AUTO_PCH_ENABLE_1 DISABLED ENUM_AUTO_PCH_ENABLE_2 DISABLED ENUM_AUTO_PCH_ENABLE_3 DISABLED ENUM_AUTO_PCH_ENABLE_4 DISABLED ENUM_AUTO_PCH_ENABLE_5 DISABLED ENUM_CAL_REQ DISABLED ENUM_CFG_BURST_LENGTH BL_8 ENUM_CFG_INTERFACE_WIDTH DWIDTH_16 ENUM_CFG_SELF_RFSH_EXIT_CYCLES SELF_RFSH_EXIT_CYCLES_512 ENUM_CFG_STARVE_LIMIT STARVE_LIMIT_4 ENUM_CFG_TYPE DDR3 ENUM_CLOCK_OFF_0 DISABLED ENUM_CLOCK_OFF_1 DISABLED ENUM_CLOCK_OFF_2 DISABLED ENUM_CLOCK_OFF_3 DISABLED ENUM_CLOCK_OFF_4 DISABLED ENUM_CLOCK_OFF_5 DISABLED ENUM_CLR_INTR NO_CLR_INTR ENUM_CMD_PORT_IN_USE_0 TRUE ENUM_CMD_PORT_IN_USE_1 FALSE ENUM_CMD_PORT_IN_USE_2 FALSE ENUM_CMD_PORT_IN_USE_3 FALSE ENUM_CMD_PORT_IN_USE_4 FALSE ENUM_CMD_PORT_IN_USE_5 FALSE ENUM_CPORT0_RDY_ALMOST_FULL NOT_FULL ENUM_CPORT0_RFIFO_MAP FIFO_0 ENUM_CPORT0_TYPE BI_DIRECTION ENUM_CPORT0_WFIFO_MAP FIFO_0 ENUM_CPORT1_RDY_ALMOST_FULL NOT_FULL ENUM_CPORT1_RFIFO_MAP FIFO_0 ENUM_CPORT1_TYPE DISABLE ENUM_CPORT1_WFIFO_MAP FIFO_0 ENUM_CPORT2_RDY_ALMOST_FULL NOT_FULL ENUM_CPORT2_RFIFO_MAP FIFO_0 ENUM_CPORT2_TYPE DISABLE ENUM_CPORT2_WFIFO_MAP FIFO_0 ENUM_CPORT3_RDY_ALMOST_FULL NOT_FULL ENUM_CPORT3_RFIFO_MAP FIFO_0 ENUM_CPORT3_TYPE DISABLE ENUM_CPORT3_WFIFO_MAP FIFO_0 ENUM_CPORT4_RDY_ALMOST_FULL NOT_FULL ENUM_CPORT4_RFIFO_MAP FIFO_0 ENUM_CPORT4_TYPE DISABLE ENUM_CPORT4_WFIFO_MAP FIFO_0 ENUM_CPORT5_RDY_ALMOST_FULL NOT_FULL ENUM_CPORT5_RFIFO_MAP FIFO_0 ENUM_CPORT5_TYPE DISABLE ENUM_CPORT5_WFIFO_MAP FIFO_0 ENUM_CTL_ADDR_ORDER CHIP_ROW_BANK_COL ENUM_CTL_ECC_ENABLED CTL_ECC_DISABLED ENUM_CTL_ECC_RMW_ENABLED CTL_ECC_RMW_DISABLED ENUM_CTL_REGDIMM_ENABLED REGDIMM_DISABLED ENUM_CTL_USR_REFRESH CTL_USR_REFRESH_ENABLED ENUM_CTRL_WIDTH DATA_WIDTH_32_BIT ENUM_DELAY_BONDING BONDING_LATENCY_0 ENUM_DFX_BYPASS_ENABLE DFX_BYPASS_DISABLED ENUM_DISABLE_MERGING MERGING_ENABLED ENUM_ECC_DQ_WIDTH ECC_DQ_WIDTH_0 ENUM_ENABLE_ATPG DISABLED ENUM_ENABLE_BONDING_0 DISABLED ENUM_ENABLE_BONDING_1 DISABLED ENUM_ENABLE_BONDING_2 DISABLED ENUM_ENABLE_BONDING_3 DISABLED ENUM_ENABLE_BONDING_4 DISABLED ENUM_ENABLE_BONDING_5 DISABLED ENUM_ENABLE_BONDING_WRAPBACK DISABLED ENUM_ENABLE_DQS_TRACKING DISABLED ENUM_ENABLE_ECC_CODE_OVERWRITES DISABLED ENUM_ENABLE_FAST_EXIT_PPD DISABLED ENUM_ENABLE_INTR DISABLED ENUM_ENABLE_NO_DM DISABLED ENUM_ENABLE_PIPELINEGLOBAL DISABLED ENUM_GANGED_ARF DISABLED ENUM_GEN_DBE GEN_DBE_DISABLED ENUM_GEN_SBE GEN_SBE_DISABLED ENUM_INC_SYNC FIFO_SET_2 ENUM_LOCAL_IF_CS_WIDTH ADDR_WIDTH_0 ENUM_MASK_CORR_DROPPED_INTR DISABLED ENUM_MASK_DBE_INTR DISABLED ENUM_MASK_SBE_INTR DISABLED ENUM_MEM_IF_AL AL_0 ENUM_MEM_IF_BANKADDR_WIDTH ADDR_WIDTH_3 ENUM_MEM_IF_BURSTLENGTH MEM_IF_BURSTLENGTH_8 ENUM_MEM_IF_COLADDR_WIDTH ADDR_WIDTH_10 ENUM_MEM_IF_CS_PER_RANK MEM_IF_CS_PER_RANK_1 ENUM_MEM_IF_CS_WIDTH MEM_IF_CS_WIDTH_1 ENUM_MEM_IF_DQ_PER_CHIP MEM_IF_DQ_PER_CHIP_8 ENUM_MEM_IF_DQS_WIDTH DQS_WIDTH_2 ENUM_MEM_IF_DWIDTH MEM_IF_DWIDTH_16 ENUM_MEM_IF_MEMTYPE DDR3_SDRAM ENUM_MEM_IF_ROWADDR_WIDTH ADDR_WIDTH_15 ENUM_MEM_IF_SPEEDBIN DDR3_1600_8_8_8 ENUM_MEM_IF_TCCD TCCD_4 ENUM_MEM_IF_TCL TCL_7 ENUM_MEM_IF_TCWL TCWL_6 ENUM_MEM_IF_TFAW TFAW_15 ENUM_MEM_IF_TMRD TMRD_4 ENUM_MEM_IF_TRAS TRAS_12 ENUM_MEM_IF_TRC TRC_17 ENUM_MEM_IF_TRCD TRCD_5 ENUM_MEM_IF_TRP TRP_5 ENUM_MEM_IF_TRRD TRRD_3 ENUM_MEM_IF_TRTP TRTP_3 ENUM_MEM_IF_TWR TWR_5 ENUM_MEM_IF_TWTR TWTR_6 ENUM_MMR_CFG_MEM_BL MP_BL_8 ENUM_OUTPUT_REGD DISABLED ENUM_PDN_EXIT_CYCLES SLOW_EXIT ENUM_PORT0_WIDTH PORT_32_BIT ENUM_PORT1_WIDTH PORT_32_BIT ENUM_PORT2_WIDTH PORT_32_BIT ENUM_PORT3_WIDTH PORT_32_BIT ENUM_PORT4_WIDTH PORT_32_BIT ENUM_PORT5_WIDTH PORT_32_BIT ENUM_PRIORITY_0_0 WEIGHT_0 ENUM_PRIORITY_0_1 WEIGHT_0 ENUM_PRIORITY_0_2 WEIGHT_0 ENUM_PRIORITY_0_3 WEIGHT_0 ENUM_PRIORITY_0_4 WEIGHT_0 ENUM_PRIORITY_0_5 WEIGHT_0 ENUM_PRIORITY_1_0 WEIGHT_0 ENUM_PRIORITY_1_1 WEIGHT_0 ENUM_PRIORITY_1_2 WEIGHT_0 ENUM_PRIORITY_1_3 WEIGHT_0 ENUM_PRIORITY_1_4 WEIGHT_0 ENUM_PRIORITY_1_5 WEIGHT_0 ENUM_PRIORITY_2_0 WEIGHT_0 ENUM_PRIORITY_2_1 WEIGHT_0 ENUM_PRIORITY_2_2 WEIGHT_0 ENUM_PRIORITY_2_3 WEIGHT_0 ENUM_PRIORITY_2_4 WEIGHT_0 ENUM_PRIORITY_2_5 WEIGHT_0 ENUM_PRIORITY_3_0 WEIGHT_0 ENUM_PRIORITY_3_1 WEIGHT_0 ENUM_PRIORITY_3_2 WEIGHT_0 ENUM_PRIORITY_3_3 WEIGHT_0 ENUM_PRIORITY_3_4 WEIGHT_0 ENUM_PRIORITY_3_5 WEIGHT_0 ENUM_PRIORITY_4_0 WEIGHT_0 ENUM_PRIORITY_4_1 WEIGHT_0 ENUM_PRIORITY_4_2 WEIGHT_0 ENUM_PRIORITY_4_3 WEIGHT_0 ENUM_PRIORITY_4_4 WEIGHT_0 ENUM_PRIORITY_4_5 WEIGHT_0 ENUM_PRIORITY_5_0 WEIGHT_0 ENUM_PRIORITY_5_1 WEIGHT_0 ENUM_PRIORITY_5_2 WEIGHT_0 ENUM_PRIORITY_5_3 WEIGHT_0 ENUM_PRIORITY_5_4 WEIGHT_0 ENUM_PRIORITY_5_5 WEIGHT_0 ENUM_PRIORITY_6_0 WEIGHT_0 ENUM_PRIORITY_6_1 WEIGHT_0 ENUM_PRIORITY_6_2 WEIGHT_0 ENUM_PRIORITY_6_3 WEIGHT_0 ENUM_PRIORITY_6_4 WEIGHT_0 ENUM_PRIORITY_6_5 WEIGHT_0 ENUM_PRIORITY_7_0 WEIGHT_0 ENUM_PRIORITY_7_1 WEIGHT_0 ENUM_PRIORITY_7_2 WEIGHT_0 ENUM_PRIORITY_7_3 WEIGHT_0 ENUM_PRIORITY_7_4 WEIGHT_0 ENUM_PRIORITY_7_5 WEIGHT_0 ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 ENUM_RD_DWIDTH_0 DWIDTH_32 ENUM_RD_DWIDTH_1 DWIDTH_0 ENUM_RD_DWIDTH_2 DWIDTH_0 ENUM_RD_DWIDTH_3 DWIDTH_0 ENUM_RD_DWIDTH_4 DWIDTH_0 ENUM_RD_DWIDTH_5 DWIDTH_0 ENUM_RD_FIFO_IN_USE_0 TRUE ENUM_RD_FIFO_IN_USE_1 FALSE ENUM_RD_FIFO_IN_USE_2 FALSE ENUM_RD_FIFO_IN_USE_3 FALSE ENUM_RD_PORT_INFO_0 USE_0 ENUM_RD_PORT_INFO_1 USE_NO ENUM_RD_PORT_INFO_2 USE_NO ENUM_RD_PORT_INFO_3 USE_NO ENUM_RD_PORT_INFO_4 USE_NO ENUM_RD_PORT_INFO_5 USE_NO ENUM_READ_ODT_CHIP ODT_DISABLED ENUM_REORDER_DATA NO_DATA_REORDERING ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 ENUM_SINGLE_READY_0 CONCATENATE_RDY ENUM_SINGLE_READY_1 CONCATENATE_RDY ENUM_SINGLE_READY_2 CONCATENATE_RDY ENUM_SINGLE_READY_3 CONCATENATE_RDY ENUM_STATIC_WEIGHT_0 WEIGHT_0 ENUM_STATIC_WEIGHT_1 WEIGHT_0 ENUM_STATIC_WEIGHT_2 WEIGHT_0 ENUM_STATIC_WEIGHT_3 WEIGHT_0 ENUM_STATIC_WEIGHT_4 WEIGHT_0 ENUM_STATIC_WEIGHT_5 WEIGHT_0 ENUM_SYNC_MODE_0 ASYNCHRONOUS ENUM_SYNC_MODE_1 ASYNCHRONOUS ENUM_SYNC_MODE_2 ASYNCHRONOUS ENUM_SYNC_MODE_3 ASYNCHRONOUS ENUM_SYNC_MODE_4 ASYNCHRONOUS ENUM_SYNC_MODE_5 ASYNCHRONOUS ENUM_TEST_MODE NORMAL_MODE ENUM_THLD_JAR1_0 THRESHOLD_32 ENUM_THLD_JAR1_1 THRESHOLD_32 ENUM_THLD_JAR1_2 THRESHOLD_32 ENUM_THLD_JAR1_3 THRESHOLD_32 ENUM_THLD_JAR1_4 THRESHOLD_32 ENUM_THLD_JAR1_5 THRESHOLD_32 ENUM_THLD_JAR2_0 THRESHOLD_16 ENUM_THLD_JAR2_1 THRESHOLD_16 ENUM_THLD_JAR2_2 THRESHOLD_16 ENUM_THLD_JAR2_3 THRESHOLD_16 ENUM_THLD_JAR2_4 THRESHOLD_16 ENUM_THLD_JAR2_5 THRESHOLD_16 ENUM_USE_ALMOST_EMPTY_0 EMPTY ENUM_USE_ALMOST_EMPTY_1 EMPTY ENUM_USE_ALMOST_EMPTY_2 EMPTY ENUM_USE_ALMOST_EMPTY_3 EMPTY ENUM_USER_ECC_EN DISABLE ENUM_USER_PRIORITY_0 PRIORITY_1 ENUM_USER_PRIORITY_1 PRIORITY_1 ENUM_USER_PRIORITY_2 PRIORITY_1 ENUM_USER_PRIORITY_3 PRIORITY_1 ENUM_USER_PRIORITY_4 PRIORITY_1 ENUM_USER_PRIORITY_5 PRIORITY_1 ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 ENUM_WFIFO0_RDY_ALMOST_FULL NOT_FULL ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 ENUM_WFIFO1_RDY_ALMOST_FULL NOT_FULL ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 ENUM_WFIFO2_RDY_ALMOST_FULL NOT_FULL ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 ENUM_WFIFO3_RDY_ALMOST_FULL NOT_FULL ENUM_WR_DWIDTH_0 DWIDTH_32 ENUM_WR_DWIDTH_1 DWIDTH_0 ENUM_WR_DWIDTH_2 DWIDTH_0 ENUM_WR_DWIDTH_3 DWIDTH_0 ENUM_WR_DWIDTH_4 DWIDTH_0 ENUM_WR_DWIDTH_5 DWIDTH_0 ENUM_WR_FIFO_IN_USE_0 TRUE ENUM_WR_FIFO_IN_USE_1 FALSE ENUM_WR_FIFO_IN_USE_2 FALSE ENUM_WR_FIFO_IN_USE_3 FALSE ENUM_WR_PORT_INFO_0 USE_0 ENUM_WR_PORT_INFO_1 USE_NO ENUM_WR_PORT_INFO_2 USE_NO ENUM_WR_PORT_INFO_3 USE_NO ENUM_WR_PORT_INFO_4 USE_NO ENUM_WR_PORT_INFO_5 USE_NO ENUM_WRITE_ODT_CHIP WRITE_CHIP0_ODT0_CHIP1 INTG_MEM_AUTO_PD_CYCLES 0 INTG_CYC_TO_RLD_JARS_0 1 INTG_CYC_TO_RLD_JARS_1 1 INTG_CYC_TO_RLD_JARS_2 1 INTG_CYC_TO_RLD_JARS_3 1 INTG_CYC_TO_RLD_JARS_4 1 INTG_CYC_TO_RLD_JARS_5 1 INTG_EXTRA_CTL_CLK_ACT_TO_ACT 0 INTG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK 0 INTG_EXTRA_CTL_CLK_ACT_TO_PCH 0 INTG_EXTRA_CTL_CLK_ACT_TO_RDWR 0 INTG_EXTRA_CTL_CLK_ARF_PERIOD 0 INTG_EXTRA_CTL_CLK_ARF_TO_VALID 0 INTG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT 0 INTG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID 0 INTG_EXTRA_CTL_CLK_PCH_TO_VALID 0 INTG_EXTRA_CTL_CLK_PDN_PERIOD 0 INTG_EXTRA_CTL_CLK_PDN_TO_VALID 0 INTG_EXTRA_CTL_CLK_RD_AP_TO_VALID 0 INTG_EXTRA_CTL_CLK_RD_TO_PCH 0 INTG_EXTRA_CTL_CLK_RD_TO_RD 0 INTG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP 0 INTG_EXTRA_CTL_CLK_RD_TO_WR 2 INTG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 INTG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 INTG_EXTRA_CTL_CLK_SRF_TO_VALID 0 INTG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL 0 INTG_EXTRA_CTL_CLK_WR_AP_TO_VALID 0 INTG_EXTRA_CTL_CLK_WR_TO_PCH 0 INTG_EXTRA_CTL_CLK_WR_TO_RD 3 INTG_EXTRA_CTL_CLK_WR_TO_RD_BC 3 INTG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP 3 INTG_EXTRA_CTL_CLK_WR_TO_WR 0 INTG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP 0 INTG_MEM_IF_TREFI 2598 INTG_MEM_IF_TRFC 87 INTG_RCFG_SUM_WT_PRIORITY_0 0 INTG_RCFG_SUM_WT_PRIORITY_1 0 INTG_RCFG_SUM_WT_PRIORITY_2 0 INTG_RCFG_SUM_WT_PRIORITY_3 0 INTG_RCFG_SUM_WT_PRIORITY_4 0 INTG_RCFG_SUM_WT_PRIORITY_5 0 INTG_RCFG_SUM_WT_PRIORITY_6 0 INTG_RCFG_SUM_WT_PRIORITY_7 0 INTG_SUM_WT_PRIORITY_0 0 INTG_SUM_WT_PRIORITY_1 0 INTG_SUM_WT_PRIORITY_2 0 INTG_SUM_WT_PRIORITY_3 0 INTG_SUM_WT_PRIORITY_4 0 INTG_SUM_WT_PRIORITY_5 0 INTG_SUM_WT_PRIORITY_6 0 INTG_SUM_WT_PRIORITY_7 0 VECT_ATTR_COUNTER_ONE_MASK 0 VECT_ATTR_COUNTER_ONE_MATCH 0 VECT_ATTR_COUNTER_ZERO_MASK 0 VECT_ATTR_COUNTER_ZERO_MATCH 0 VECT_ATTR_DEBUG_SELECT_BYTE 0 INTG_POWER_SAVING_EXIT_CYCLES 5 INTG_MEM_CLK_ENTRY_CYCLES 10 ENUM_ENABLE_BURST_INTERRUPT DISABLED ENUM_ENABLE_BURST_TERMINATE DISABLED AV_PORT_0_CONNECT_TO_CV_PORT 0 CV_PORT_0_CONNECT_TO_AV_PORT 0 CV_AVL_DATA_WIDTH_PORT_0 32 CV_AVL_ADDR_WIDTH_PORT_0 27 CV_CPORT_TYPE_PORT_0 3 CV_AVL_NUM_SYMBOLS_PORT_0 4 CV_LSB_WFIFO_PORT_0 0 CV_MSB_WFIFO_PORT_0 0 CV_LSB_RFIFO_PORT_0 0 CV_MSB_RFIFO_PORT_0 0 CV_ENUM_AUTO_PCH_ENABLE_0 DISABLED CV_ENUM_CMD_PORT_IN_USE_0 TRUE CV_ENUM_CPORT0_RFIFO_MAP FIFO_0 CV_ENUM_CPORT0_TYPE BI_DIRECTION CV_ENUM_CPORT0_WFIFO_MAP FIFO_0 CV_ENUM_ENABLE_BONDING_0 DISABLED CV_ENUM_PORT0_WIDTH PORT_32_BIT CV_ENUM_PRIORITY_0_0 WEIGHT_0 CV_ENUM_PRIORITY_1_0 WEIGHT_0 CV_ENUM_PRIORITY_2_0 WEIGHT_0 CV_ENUM_PRIORITY_3_0 WEIGHT_0 CV_ENUM_PRIORITY_4_0 WEIGHT_0 CV_ENUM_PRIORITY_5_0 WEIGHT_0 CV_ENUM_PRIORITY_6_0 WEIGHT_0 CV_ENUM_PRIORITY_7_0 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_0 WEIGHT_0 CV_ENUM_RCFG_USER_PRIORITY_0 PRIORITY_1 CV_ENUM_RD_DWIDTH_0 DWIDTH_32 CV_ENUM_RD_PORT_INFO_0 USE_0 CV_ENUM_STATIC_WEIGHT_0 WEIGHT_0 CV_ENUM_USER_PRIORITY_0 PRIORITY_1 CV_ENUM_WR_DWIDTH_0 DWIDTH_32 CV_ENUM_WR_PORT_INFO_0 USE_0 TG_TEMP_PORT_0 3 AV_PORT_1_CONNECT_TO_CV_PORT 1 CV_PORT_1_CONNECT_TO_AV_PORT 1 CV_AVL_DATA_WIDTH_PORT_1 1 CV_AVL_ADDR_WIDTH_PORT_1 1 CV_CPORT_TYPE_PORT_1 0 CV_AVL_NUM_SYMBOLS_PORT_1 1 CV_LSB_WFIFO_PORT_1 5 CV_MSB_WFIFO_PORT_1 5 CV_LSB_RFIFO_PORT_1 5 CV_MSB_RFIFO_PORT_1 5 CV_ENUM_AUTO_PCH_ENABLE_1 DISABLED CV_ENUM_CMD_PORT_IN_USE_1 FALSE CV_ENUM_CPORT1_RFIFO_MAP FIFO_0 CV_ENUM_CPORT1_TYPE DISABLE CV_ENUM_CPORT1_WFIFO_MAP FIFO_0 CV_ENUM_ENABLE_BONDING_1 DISABLED CV_ENUM_PORT1_WIDTH PORT_32_BIT CV_ENUM_PRIORITY_0_1 WEIGHT_0 CV_ENUM_PRIORITY_1_1 WEIGHT_0 CV_ENUM_PRIORITY_2_1 WEIGHT_0 CV_ENUM_PRIORITY_3_1 WEIGHT_0 CV_ENUM_PRIORITY_4_1 WEIGHT_0 CV_ENUM_PRIORITY_5_1 WEIGHT_0 CV_ENUM_PRIORITY_6_1 WEIGHT_0 CV_ENUM_PRIORITY_7_1 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_RCFG_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_RD_DWIDTH_1 DWIDTH_0 CV_ENUM_RD_PORT_INFO_1 USE_NO CV_ENUM_STATIC_WEIGHT_1 WEIGHT_0 CV_ENUM_USER_PRIORITY_1 PRIORITY_1 CV_ENUM_WR_DWIDTH_1 DWIDTH_0 CV_ENUM_WR_PORT_INFO_1 USE_NO TG_TEMP_PORT_1 0 AV_PORT_2_CONNECT_TO_CV_PORT 2 CV_PORT_2_CONNECT_TO_AV_PORT 2 CV_AVL_DATA_WIDTH_PORT_2 1 CV_AVL_ADDR_WIDTH_PORT_2 1 CV_CPORT_TYPE_PORT_2 0 CV_AVL_NUM_SYMBOLS_PORT_2 1 CV_LSB_WFIFO_PORT_2 5 CV_MSB_WFIFO_PORT_2 5 CV_LSB_RFIFO_PORT_2 5 CV_MSB_RFIFO_PORT_2 5 CV_ENUM_AUTO_PCH_ENABLE_2 DISABLED CV_ENUM_CMD_PORT_IN_USE_2 FALSE CV_ENUM_CPORT2_RFIFO_MAP FIFO_0 CV_ENUM_CPORT2_TYPE DISABLE CV_ENUM_CPORT2_WFIFO_MAP FIFO_0 CV_ENUM_ENABLE_BONDING_2 DISABLED CV_ENUM_PORT2_WIDTH PORT_32_BIT CV_ENUM_PRIORITY_0_2 WEIGHT_0 CV_ENUM_PRIORITY_1_2 WEIGHT_0 CV_ENUM_PRIORITY_2_2 WEIGHT_0 CV_ENUM_PRIORITY_3_2 WEIGHT_0 CV_ENUM_PRIORITY_4_2 WEIGHT_0 CV_ENUM_PRIORITY_5_2 WEIGHT_0 CV_ENUM_PRIORITY_6_2 WEIGHT_0 CV_ENUM_PRIORITY_7_2 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_2 WEIGHT_0 CV_ENUM_RCFG_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_RD_DWIDTH_2 DWIDTH_0 CV_ENUM_RD_PORT_INFO_2 USE_NO CV_ENUM_STATIC_WEIGHT_2 WEIGHT_0 CV_ENUM_USER_PRIORITY_2 PRIORITY_1 CV_ENUM_WR_DWIDTH_2 DWIDTH_0 CV_ENUM_WR_PORT_INFO_2 USE_NO TG_TEMP_PORT_2 0 AV_PORT_3_CONNECT_TO_CV_PORT 3 CV_PORT_3_CONNECT_TO_AV_PORT 3 CV_AVL_DATA_WIDTH_PORT_3 1 CV_AVL_ADDR_WIDTH_PORT_3 1 CV_CPORT_TYPE_PORT_3 0 CV_AVL_NUM_SYMBOLS_PORT_3 1 CV_LSB_WFIFO_PORT_3 5 CV_MSB_WFIFO_PORT_3 5 CV_LSB_RFIFO_PORT_3 5 CV_MSB_RFIFO_PORT_3 5 CV_ENUM_AUTO_PCH_ENABLE_3 DISABLED CV_ENUM_CMD_PORT_IN_USE_3 FALSE CV_ENUM_CPORT3_RFIFO_MAP FIFO_0 CV_ENUM_CPORT3_TYPE DISABLE CV_ENUM_CPORT3_WFIFO_MAP FIFO_0 CV_ENUM_ENABLE_BONDING_3 DISABLED CV_ENUM_PORT3_WIDTH PORT_32_BIT CV_ENUM_PRIORITY_0_3 WEIGHT_0 CV_ENUM_PRIORITY_1_3 WEIGHT_0 CV_ENUM_PRIORITY_2_3 WEIGHT_0 CV_ENUM_PRIORITY_3_3 WEIGHT_0 CV_ENUM_PRIORITY_4_3 WEIGHT_0 CV_ENUM_PRIORITY_5_3 WEIGHT_0 CV_ENUM_PRIORITY_6_3 WEIGHT_0 CV_ENUM_PRIORITY_7_3 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_RCFG_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_RD_DWIDTH_3 DWIDTH_0 CV_ENUM_RD_PORT_INFO_3 USE_NO CV_ENUM_STATIC_WEIGHT_3 WEIGHT_0 CV_ENUM_USER_PRIORITY_3 PRIORITY_1 CV_ENUM_WR_DWIDTH_3 DWIDTH_0 CV_ENUM_WR_PORT_INFO_3 USE_NO TG_TEMP_PORT_3 0 AV_PORT_4_CONNECT_TO_CV_PORT 4 CV_PORT_4_CONNECT_TO_AV_PORT 4 CV_AVL_DATA_WIDTH_PORT_4 1 CV_AVL_ADDR_WIDTH_PORT_4 1 CV_CPORT_TYPE_PORT_4 0 CV_AVL_NUM_SYMBOLS_PORT_4 1 CV_LSB_WFIFO_PORT_4 5 CV_MSB_WFIFO_PORT_4 5 CV_LSB_RFIFO_PORT_4 5 CV_MSB_RFIFO_PORT_4 5 CV_ENUM_AUTO_PCH_ENABLE_4 DISABLED CV_ENUM_CMD_PORT_IN_USE_4 FALSE CV_ENUM_CPORT4_RFIFO_MAP FIFO_0 CV_ENUM_CPORT4_TYPE DISABLE CV_ENUM_CPORT4_WFIFO_MAP FIFO_0 CV_ENUM_ENABLE_BONDING_4 DISABLED CV_ENUM_PORT4_WIDTH PORT_32_BIT CV_ENUM_PRIORITY_0_4 WEIGHT_0 CV_ENUM_PRIORITY_1_4 WEIGHT_0 CV_ENUM_PRIORITY_2_4 WEIGHT_0 CV_ENUM_PRIORITY_3_4 WEIGHT_0 CV_ENUM_PRIORITY_4_4 WEIGHT_0 CV_ENUM_PRIORITY_5_4 WEIGHT_0 CV_ENUM_PRIORITY_6_4 WEIGHT_0 CV_ENUM_PRIORITY_7_4 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_RCFG_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_RD_DWIDTH_4 DWIDTH_0 CV_ENUM_RD_PORT_INFO_4 USE_NO CV_ENUM_STATIC_WEIGHT_4 WEIGHT_0 CV_ENUM_USER_PRIORITY_4 PRIORITY_1 CV_ENUM_WR_DWIDTH_4 DWIDTH_0 CV_ENUM_WR_PORT_INFO_4 USE_NO TG_TEMP_PORT_4 0 AV_PORT_5_CONNECT_TO_CV_PORT 5 CV_PORT_5_CONNECT_TO_AV_PORT 5 CV_AVL_DATA_WIDTH_PORT_5 1 CV_AVL_ADDR_WIDTH_PORT_5 1 CV_CPORT_TYPE_PORT_5 0 CV_AVL_NUM_SYMBOLS_PORT_5 1 CV_LSB_WFIFO_PORT_5 5 CV_MSB_WFIFO_PORT_5 5 CV_LSB_RFIFO_PORT_5 5 CV_MSB_RFIFO_PORT_5 5 CV_ENUM_AUTO_PCH_ENABLE_5 DISABLED CV_ENUM_CMD_PORT_IN_USE_5 FALSE CV_ENUM_CPORT5_RFIFO_MAP FIFO_0 CV_ENUM_CPORT5_TYPE DISABLE CV_ENUM_CPORT5_WFIFO_MAP FIFO_0 CV_ENUM_ENABLE_BONDING_5 DISABLED CV_ENUM_PORT5_WIDTH PORT_32_BIT CV_ENUM_PRIORITY_0_5 WEIGHT_0 CV_ENUM_PRIORITY_1_5 WEIGHT_0 CV_ENUM_PRIORITY_2_5 WEIGHT_0 CV_ENUM_PRIORITY_3_5 WEIGHT_0 CV_ENUM_PRIORITY_4_5 WEIGHT_0 CV_ENUM_PRIORITY_5_5 WEIGHT_0 CV_ENUM_PRIORITY_6_5 WEIGHT_0 CV_ENUM_PRIORITY_7_5 WEIGHT_0 CV_ENUM_RCFG_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_RCFG_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_RD_DWIDTH_5 DWIDTH_0 CV_ENUM_RD_PORT_INFO_5 USE_NO CV_ENUM_STATIC_WEIGHT_5 WEIGHT_0 CV_ENUM_USER_PRIORITY_5 PRIORITY_1 CV_ENUM_WR_DWIDTH_5 DWIDTH_0 CV_ENUM_WR_PORT_INFO_5 USE_NO TG_TEMP_PORT_5 0 CV_ENUM_RFIFO0_CPORT_MAP CMD_PORT_0 CV_ENUM_WFIFO0_CPORT_MAP CMD_PORT_0 CV_ENUM_RFIFO1_CPORT_MAP CMD_PORT_0 CV_ENUM_WFIFO1_CPORT_MAP CMD_PORT_0 CV_ENUM_RFIFO2_CPORT_MAP CMD_PORT_0 CV_ENUM_WFIFO2_CPORT_MAP CMD_PORT_0 CV_ENUM_RFIFO3_CPORT_MAP CMD_PORT_0 CV_ENUM_WFIFO3_CPORT_MAP CMD_PORT_0 CV_INTG_RCFG_SUM_WT_PRIORITY_0 0 CV_INTG_SUM_WT_PRIORITY_0 0 CV_INTG_RCFG_SUM_WT_PRIORITY_1 0 CV_INTG_SUM_WT_PRIORITY_1 0 CV_INTG_RCFG_SUM_WT_PRIORITY_2 0 CV_INTG_SUM_WT_PRIORITY_2 0 CV_INTG_RCFG_SUM_WT_PRIORITY_3 0 CV_INTG_SUM_WT_PRIORITY_3 0 CV_INTG_RCFG_SUM_WT_PRIORITY_4 0 CV_INTG_SUM_WT_PRIORITY_4 0 CV_INTG_RCFG_SUM_WT_PRIORITY_5 0 CV_INTG_SUM_WT_PRIORITY_5 0 CV_INTG_RCFG_SUM_WT_PRIORITY_6 0 CV_INTG_SUM_WT_PRIORITY_6 0 CV_INTG_RCFG_SUM_WT_PRIORITY_7 0 CV_INTG_SUM_WT_PRIORITY_7 0 CONTINUE_AFTER_CAL_FAIL false MAX10_CFG false POWER_OF_TWO_BUS false SOPC_COMPAT_RESET false AVL_MAX_SIZE 4 BYTE_ENABLE true ENABLE_CTRL_AVALON_INTERFACE true CTL_DEEP_POWERDN_EN false CTL_SELF_REFRESH_EN false AUTO_POWERDN_EN false AUTO_PD_CYCLES 0 CTL_USR_REFRESH_EN true CTL_AUTOPCH_EN false CTL_ZQCAL_EN false ADDR_ORDER 0 CTL_LOOK_AHEAD_DEPTH 4 CONTROLLER_LATENCY 5 CFG_REORDER_DATA false STARVE_LIMIT 10 CTL_CSR_ENABLED false CTL_CSR_CONNECTION INTERNAL_JTAG CTL_ECC_ENABLED false CTL_HRB_ENABLED false CTL_ECC_AUTO_CORRECTION_ENABLED false MULTICAST_EN false CTL_DYNAMIC_BANK_ALLOCATION false CTL_DYNAMIC_BANK_NUM 4 DEBUG_MODE false ENABLE_BURST_MERGE false CTL_ENABLE_BURST_INTERRUPT false CTL_ENABLE_BURST_TERMINATE false LOCAL_ID_WIDTH 8 RDBUFFER_ADDR_WIDTH 8 WRBUFFER_ADDR_WIDTH 6 MAX_PENDING_WR_CMD 16 MAX_PENDING_RD_CMD 32 USE_MM_ADAPTOR true USE_AXI_ADAPTOR false HCX_COMPAT_MODE false CTL_CMD_QUEUE_DEPTH 8 CTL_CSR_READ_ONLY 1 CFG_DATA_REORDERING_TYPE INTER_BANK NUM_OF_PORTS 1 ENABLE_BONDING false ENABLE_USER_ECC false AVL_DATA_WIDTH_PORT 32,32,32,32,32,32 PRIORITY_PORT 1,1,1,1,1,1 WEIGHT_PORT 0,0,0,0,0,0 CPORT_TYPE_PORT Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional,Bidirectional CORE_PERIPHERY_DUAL_CLOCK false USE_DR_CLK false DLL_USE_DR_CLK false USE_2X_FF false DUAL_WRITE_CLOCK false GENERIC_PLL true USE_HARD_READ_FIFO false READ_FIFO_HALF_RATE false PLL_MASTER true DLL_MASTER true PHY_VERSION_NUMBER 231 ENABLE_NIOS_OCI false ENABLE_EMIT_JTAG_MASTER false ENABLE_NIOS_JTAG_UART false ENABLE_NIOS_PRINTF_OUTPUT false ENABLE_LARGE_RW_MGR_DI_BUFFER false ENABLE_EMIT_BFM_MASTER false FORCE_SEQUENCER_TCL_DEBUG_MODE false ENABLE_SEQUENCER_MARGINING_ON_BY_DEFAULT false ENABLE_MAX_SIZE_SEQ_MEM false MAKE_INTERNAL_NIOS_VISIBLE false DEPLOY_SEQUENCER_SW_FILES_FOR_DEBUG false ENABLE_CSR_SOFT_RESET_REQ false DUPLICATE_PLL_FOR_PHY_CLK true MAX_LATENCY_COUNT_WIDTH 5 READ_VALID_FIFO_SIZE 16 EXTRA_VFIFO_SHIFT 0 TB_MEM_CLK_FREQ 333.0 TB_RATE FULL TB_MEM_IF_DQ_WIDTH 16 TB_MEM_IF_READ_DQS_WIDTH 2 TB_PLL_DLL_MASTER true FAST_SIM_CALIBRATION false REF_CLK_FREQ 50.0 REF_CLK_FREQ_STR 50.0 MHz REF_CLK_NS 20.0 REF_CLK_PS 20000.0 PLL_DR_CLK_FREQ 0.0 PLL_DR_CLK_FREQ_STR PLL_DR_CLK_FREQ_SIM_STR 0 ps PLL_DR_CLK_PHASE_PS 0 PLL_DR_CLK_PHASE_PS_STR PLL_DR_CLK_PHASE_DEG 0.0 PLL_DR_CLK_PHASE_PS_SIM 0 PLL_DR_CLK_PHASE_PS_SIM_STR PLL_DR_CLK_PHASE_DEG_SIM 0.0 PLL_DR_CLK_MULT 0 PLL_DR_CLK_DIV 0 PLL_MEM_CLK_FREQ 333.333333 PLL_MEM_CLK_FREQ_STR 333.333333 MHz PLL_MEM_CLK_FREQ_SIM_STR 3004 ps PLL_MEM_CLK_PHASE_PS 0 PLL_MEM_CLK_PHASE_PS_STR 0 ps PLL_MEM_CLK_PHASE_DEG 0.0 PLL_MEM_CLK_PHASE_PS_SIM 0 PLL_MEM_CLK_PHASE_PS_SIM_STR 0 ps PLL_MEM_CLK_PHASE_DEG_SIM 0.0 PLL_MEM_CLK_MULT 6666666 PLL_MEM_CLK_DIV 1000000 PLL_AFI_CLK_FREQ 333.333333 PLL_AFI_CLK_FREQ_STR 333.333333 MHz PLL_AFI_CLK_FREQ_SIM_STR 3004 ps PLL_AFI_CLK_PHASE_PS 0 PLL_AFI_CLK_PHASE_PS_STR 0 ps PLL_AFI_CLK_PHASE_DEG 0.0 PLL_AFI_CLK_PHASE_PS_SIM 0 PLL_AFI_CLK_PHASE_PS_SIM_STR 0 ps PLL_AFI_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_CLK_MULT 6666666 PLL_AFI_CLK_DIV 1000000 PLL_WRITE_CLK_FREQ 333.333333 PLL_WRITE_CLK_FREQ_STR 333.333333 MHz PLL_WRITE_CLK_FREQ_SIM_STR 3004 ps PLL_WRITE_CLK_PHASE_PS 2250 PLL_WRITE_CLK_PHASE_PS_STR 2250 ps PLL_WRITE_CLK_PHASE_DEG 270.0 PLL_WRITE_CLK_PHASE_PS_SIM 2252 PLL_WRITE_CLK_PHASE_PS_SIM_STR 2252 ps PLL_WRITE_CLK_PHASE_DEG_SIM 270.0 PLL_WRITE_CLK_MULT 6666666 PLL_WRITE_CLK_DIV 1000000 PLL_ADDR_CMD_CLK_FREQ 333.333333 PLL_ADDR_CMD_CLK_FREQ_STR 333.333333 MHz PLL_ADDR_CMD_CLK_FREQ_SIM_STR 3004 ps PLL_ADDR_CMD_CLK_PHASE_PS 2250 PLL_ADDR_CMD_CLK_PHASE_PS_STR 2250 ps PLL_ADDR_CMD_CLK_PHASE_DEG 270.0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM 2252 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR 2252 ps PLL_ADDR_CMD_CLK_PHASE_DEG_SIM 270.0 PLL_ADDR_CMD_CLK_MULT 6666666 PLL_ADDR_CMD_CLK_DIV 1000000 PLL_AFI_HALF_CLK_FREQ 166.666666 PLL_AFI_HALF_CLK_FREQ_STR 166.666666 MHz PLL_AFI_HALF_CLK_FREQ_SIM_STR 6008 ps PLL_AFI_HALF_CLK_PHASE_PS 0 PLL_AFI_HALF_CLK_PHASE_PS_STR 0 ps PLL_AFI_HALF_CLK_PHASE_DEG 0.0 PLL_AFI_HALF_CLK_PHASE_PS_SIM 0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR 0 ps PLL_AFI_HALF_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_HALF_CLK_MULT 6666666 PLL_AFI_HALF_CLK_DIV 2000000 PLL_NIOS_CLK_FREQ 66.666666 PLL_NIOS_CLK_FREQ_STR 66.666666 MHz PLL_NIOS_CLK_FREQ_SIM_STR 15020 ps PLL_NIOS_CLK_PHASE_PS 375 PLL_NIOS_CLK_PHASE_PS_STR 375 ps PLL_NIOS_CLK_PHASE_DEG 9.0 PLL_NIOS_CLK_PHASE_PS_SIM 417 PLL_NIOS_CLK_PHASE_PS_SIM_STR 417 ps PLL_NIOS_CLK_PHASE_DEG_SIM 10.0 PLL_NIOS_CLK_MULT 6666666 PLL_NIOS_CLK_DIV 5000000 PLL_CONFIG_CLK_FREQ 22.222222 PLL_CONFIG_CLK_FREQ_STR 22.222222 MHz PLL_CONFIG_CLK_FREQ_SIM_STR 45060 ps PLL_CONFIG_CLK_PHASE_PS 0 PLL_CONFIG_CLK_PHASE_PS_STR 0 ps PLL_CONFIG_CLK_PHASE_DEG 0.0 PLL_CONFIG_CLK_PHASE_PS_SIM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR 0 ps PLL_CONFIG_CLK_PHASE_DEG_SIM 0.0 PLL_CONFIG_CLK_MULT 6666666 PLL_CONFIG_CLK_DIV 15000000 PLL_P2C_READ_CLK_FREQ 0.0 PLL_P2C_READ_CLK_FREQ_STR PLL_P2C_READ_CLK_FREQ_SIM_STR 0 ps PLL_P2C_READ_CLK_PHASE_PS 0 PLL_P2C_READ_CLK_PHASE_PS_STR PLL_P2C_READ_CLK_PHASE_DEG 0.0 PLL_P2C_READ_CLK_PHASE_PS_SIM 0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR PLL_P2C_READ_CLK_PHASE_DEG_SIM 0.0 PLL_P2C_READ_CLK_MULT 0 PLL_P2C_READ_CLK_DIV 0 PLL_C2P_WRITE_CLK_FREQ 0.0 PLL_C2P_WRITE_CLK_FREQ_STR PLL_C2P_WRITE_CLK_FREQ_SIM_STR 0 ps PLL_C2P_WRITE_CLK_PHASE_PS 0 PLL_C2P_WRITE_CLK_PHASE_PS_STR PLL_C2P_WRITE_CLK_PHASE_DEG 0.0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR PLL_C2P_WRITE_CLK_PHASE_DEG_SIM 0.0 PLL_C2P_WRITE_CLK_MULT 0 PLL_C2P_WRITE_CLK_DIV 0 PLL_HR_CLK_FREQ 0.0 PLL_HR_CLK_FREQ_STR PLL_HR_CLK_FREQ_SIM_STR 0 ps PLL_HR_CLK_PHASE_PS 0 PLL_HR_CLK_PHASE_PS_STR PLL_HR_CLK_PHASE_DEG 0.0 PLL_HR_CLK_PHASE_PS_SIM 0 PLL_HR_CLK_PHASE_PS_SIM_STR PLL_HR_CLK_PHASE_DEG_SIM 0.0 PLL_HR_CLK_MULT 0 PLL_HR_CLK_DIV 0 PLL_AFI_PHY_CLK_FREQ 333.333333 PLL_AFI_PHY_CLK_FREQ_STR 333.333333 MHz PLL_AFI_PHY_CLK_FREQ_SIM_STR 3004 ps PLL_AFI_PHY_CLK_PHASE_PS 0 PLL_AFI_PHY_CLK_PHASE_PS_STR 0 ps PLL_AFI_PHY_CLK_PHASE_DEG 0.0 PLL_AFI_PHY_CLK_PHASE_PS_SIM 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR 0 ps PLL_AFI_PHY_CLK_PHASE_DEG_SIM 0.0 PLL_AFI_PHY_CLK_MULT 6666666 PLL_AFI_PHY_CLK_DIV 1000000 REF_CLK_FREQ_CACHE_VALID true REF_CLK_FREQ_PARAM_VALID false REF_CLK_FREQ_MIN_PARAM 0.0 REF_CLK_FREQ_MAX_PARAM 0.0 REF_CLK_FREQ_MIN_CACHE 10.0 REF_CLK_FREQ_MAX_CACHE 500.0 PLL_DR_CLK_FREQ_PARAM 0.0 PLL_DR_CLK_FREQ_SIM_STR_PARAM PLL_DR_CLK_PHASE_PS_PARAM 0 PLL_DR_CLK_PHASE_PS_SIM_STR_PARAM PLL_DR_CLK_MULT_PARAM 0 PLL_DR_CLK_DIV_PARAM 0 PLL_DR_CLK_FREQ_CACHE 0.0 PLL_DR_CLK_FREQ_SIM_STR_CACHE PLL_DR_CLK_PHASE_PS_CACHE 0 PLL_DR_CLK_PHASE_PS_SIM_STR_CACHE PLL_DR_CLK_MULT_CACHE 0 PLL_DR_CLK_DIV_CACHE 0 PLL_MEM_CLK_FREQ_PARAM 0.0 PLL_MEM_CLK_FREQ_SIM_STR_PARAM PLL_MEM_CLK_PHASE_PS_PARAM 0 PLL_MEM_CLK_PHASE_PS_SIM_STR_PARAM PLL_MEM_CLK_MULT_PARAM 0 PLL_MEM_CLK_DIV_PARAM 0 PLL_MEM_CLK_FREQ_CACHE 333.333333 PLL_MEM_CLK_FREQ_SIM_STR_CACHE 3004 ps PLL_MEM_CLK_PHASE_PS_CACHE 0 PLL_MEM_CLK_PHASE_PS_SIM_STR_CACHE 0 ps PLL_MEM_CLK_MULT_CACHE 6666666 PLL_MEM_CLK_DIV_CACHE 1000000 PLL_AFI_CLK_FREQ_PARAM 0.0 PLL_AFI_CLK_FREQ_SIM_STR_PARAM PLL_AFI_CLK_PHASE_PS_PARAM 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_PARAM PLL_AFI_CLK_MULT_PARAM 0 PLL_AFI_CLK_DIV_PARAM 0 PLL_AFI_CLK_FREQ_CACHE 333.333333 PLL_AFI_CLK_FREQ_SIM_STR_CACHE 3004 ps PLL_AFI_CLK_PHASE_PS_CACHE 0 PLL_AFI_CLK_PHASE_PS_SIM_STR_CACHE 0 ps PLL_AFI_CLK_MULT_CACHE 6666666 PLL_AFI_CLK_DIV_CACHE 1000000 PLL_WRITE_CLK_FREQ_PARAM 0.0 PLL_WRITE_CLK_FREQ_SIM_STR_PARAM PLL_WRITE_CLK_PHASE_PS_PARAM 0 PLL_WRITE_CLK_PHASE_PS_SIM_STR_PARAM PLL_WRITE_CLK_MULT_PARAM 0 PLL_WRITE_CLK_DIV_PARAM 0 PLL_WRITE_CLK_FREQ_CACHE 333.333333 PLL_WRITE_CLK_FREQ_SIM_STR_CACHE 3004 ps PLL_WRITE_CLK_PHASE_PS_CACHE 2250 PLL_WRITE_CLK_PHASE_PS_SIM_STR_CACHE 2252 ps PLL_WRITE_CLK_MULT_CACHE 6666666 PLL_WRITE_CLK_DIV_CACHE 1000000 PLL_ADDR_CMD_CLK_FREQ_PARAM 0.0 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_PARAM PLL_ADDR_CMD_CLK_PHASE_PS_PARAM 0 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_PARAM PLL_ADDR_CMD_CLK_MULT_PARAM 0 PLL_ADDR_CMD_CLK_DIV_PARAM 0 PLL_ADDR_CMD_CLK_FREQ_CACHE 333.333333 PLL_ADDR_CMD_CLK_FREQ_SIM_STR_CACHE 3004 ps PLL_ADDR_CMD_CLK_PHASE_PS_CACHE 2250 PLL_ADDR_CMD_CLK_PHASE_PS_SIM_STR_CACHE 2252 ps PLL_ADDR_CMD_CLK_MULT_CACHE 6666666 PLL_ADDR_CMD_CLK_DIV_CACHE 1000000 PLL_AFI_HALF_CLK_FREQ_PARAM 0.0 PLL_AFI_HALF_CLK_FREQ_SIM_STR_PARAM PLL_AFI_HALF_CLK_PHASE_PS_PARAM 0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_PARAM PLL_AFI_HALF_CLK_MULT_PARAM 0 PLL_AFI_HALF_CLK_DIV_PARAM 0 PLL_AFI_HALF_CLK_FREQ_CACHE 166.666666 PLL_AFI_HALF_CLK_FREQ_SIM_STR_CACHE 6008 ps PLL_AFI_HALF_CLK_PHASE_PS_CACHE 0 PLL_AFI_HALF_CLK_PHASE_PS_SIM_STR_CACHE 0 ps PLL_AFI_HALF_CLK_MULT_CACHE 6666666 PLL_AFI_HALF_CLK_DIV_CACHE 2000000 PLL_NIOS_CLK_FREQ_PARAM 0.0 PLL_NIOS_CLK_FREQ_SIM_STR_PARAM PLL_NIOS_CLK_PHASE_PS_PARAM 0 PLL_NIOS_CLK_PHASE_PS_SIM_STR_PARAM PLL_NIOS_CLK_MULT_PARAM 0 PLL_NIOS_CLK_DIV_PARAM 0 PLL_NIOS_CLK_FREQ_CACHE 66.666666 PLL_NIOS_CLK_FREQ_SIM_STR_CACHE 15020 ps PLL_NIOS_CLK_PHASE_PS_CACHE 375 PLL_NIOS_CLK_PHASE_PS_SIM_STR_CACHE 417 ps PLL_NIOS_CLK_MULT_CACHE 6666666 PLL_NIOS_CLK_DIV_CACHE 5000000 PLL_CONFIG_CLK_FREQ_PARAM 0.0 PLL_CONFIG_CLK_FREQ_SIM_STR_PARAM PLL_CONFIG_CLK_PHASE_PS_PARAM 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_PARAM PLL_CONFIG_CLK_MULT_PARAM 0 PLL_CONFIG_CLK_DIV_PARAM 0 PLL_CONFIG_CLK_FREQ_CACHE 22.222222 PLL_CONFIG_CLK_FREQ_SIM_STR_CACHE 45060 ps PLL_CONFIG_CLK_PHASE_PS_CACHE 0 PLL_CONFIG_CLK_PHASE_PS_SIM_STR_CACHE 0 ps PLL_CONFIG_CLK_MULT_CACHE 6666666 PLL_CONFIG_CLK_DIV_CACHE 15000000 PLL_P2C_READ_CLK_FREQ_PARAM 0.0 PLL_P2C_READ_CLK_FREQ_SIM_STR_PARAM PLL_P2C_READ_CLK_PHASE_PS_PARAM 0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_PARAM PLL_P2C_READ_CLK_MULT_PARAM 0 PLL_P2C_READ_CLK_DIV_PARAM 0 PLL_P2C_READ_CLK_FREQ_CACHE 0.0 PLL_P2C_READ_CLK_FREQ_SIM_STR_CACHE PLL_P2C_READ_CLK_PHASE_PS_CACHE 0 PLL_P2C_READ_CLK_PHASE_PS_SIM_STR_CACHE PLL_P2C_READ_CLK_MULT_CACHE 0 PLL_P2C_READ_CLK_DIV_CACHE 0 PLL_C2P_WRITE_CLK_FREQ_PARAM 0.0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_PARAM PLL_C2P_WRITE_CLK_PHASE_PS_PARAM 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_PARAM PLL_C2P_WRITE_CLK_MULT_PARAM 0 PLL_C2P_WRITE_CLK_DIV_PARAM 0 PLL_C2P_WRITE_CLK_FREQ_CACHE 0.0 PLL_C2P_WRITE_CLK_FREQ_SIM_STR_CACHE PLL_C2P_WRITE_CLK_PHASE_PS_CACHE 0 PLL_C2P_WRITE_CLK_PHASE_PS_SIM_STR_CACHE PLL_C2P_WRITE_CLK_MULT_CACHE 0 PLL_C2P_WRITE_CLK_DIV_CACHE 0 PLL_HR_CLK_FREQ_PARAM 0.0 PLL_HR_CLK_FREQ_SIM_STR_PARAM PLL_HR_CLK_PHASE_PS_PARAM 0 PLL_HR_CLK_PHASE_PS_SIM_STR_PARAM PLL_HR_CLK_MULT_PARAM 0 PLL_HR_CLK_DIV_PARAM 0 PLL_HR_CLK_FREQ_CACHE 0.0 PLL_HR_CLK_FREQ_SIM_STR_CACHE PLL_HR_CLK_PHASE_PS_CACHE 0 PLL_HR_CLK_PHASE_PS_SIM_STR_CACHE PLL_HR_CLK_MULT_CACHE 0 PLL_HR_CLK_DIV_CACHE 0 PLL_AFI_PHY_CLK_FREQ_PARAM 0.0 PLL_AFI_PHY_CLK_FREQ_SIM_STR_PARAM PLL_AFI_PHY_CLK_PHASE_PS_PARAM 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_PARAM PLL_AFI_PHY_CLK_MULT_PARAM 0 PLL_AFI_PHY_CLK_DIV_PARAM 0 PLL_AFI_PHY_CLK_FREQ_CACHE 333.333333 PLL_AFI_PHY_CLK_FREQ_SIM_STR_CACHE 3004 ps PLL_AFI_PHY_CLK_PHASE_PS_CACHE 0 PLL_AFI_PHY_CLK_PHASE_PS_SIM_STR_CACHE 0 ps PLL_AFI_PHY_CLK_MULT_CACHE 6666666 PLL_AFI_PHY_CLK_DIV_CACHE 1000000 SPEED_GRADE_CACHE 8 IS_ES_DEVICE_CACHE false MEM_CLK_FREQ_CACHE 333.0 REF_CLK_FREQ_CACHE 50.0 RATE_CACHE Full HCX_COMPAT_MODE_CACHE false PARSE_FRIENDLY_DEVICE_FAMILY_CACHE CYCLONEV COMMAND_PHASE_CACHE 0.0 MEM_CK_PHASE_CACHE 0.0 P2C_READ_CLOCK_ADD_PHASE_CACHE 0.0 C2P_WRITE_CLOCK_ADD_PHASE_CACHE 0.0 ACV_PHY_CLK_ADD_FR_PHASE_CACHE 0.0 SEQUENCER_TYPE_CACHE NIOS USE_MEM_CLK_FREQ_CACHE false PLL_CLK_CACHE_VALID true PLL_CLK_PARAM_VALID false ENABLE_EXTRA_REPORTING false NUM_EXTRA_REPORT_PATH 10 ENABLE_ISS_PROBES false CALIB_REG_WIDTH 8 USE_SEQUENCER_BFM false PLL_SHARING_MODE None NUM_PLL_SHARING_INTERFACES 1 EXPORT_AFI_HALF_CLK true ABSTRACT_REAL_COMPARE_TEST false INCLUDE_BOARD_DELAY_MODEL false INCLUDE_MULTIRANK_BOARD_DELAY_MODEL false USE_FAKE_PHY_INTERNAL false USE_FAKE_PHY false FORCE_MAX_LATENCY_COUNT_WIDTH 0 USE_ALL_AFI_PHASES_FOR_COMMAND_ISSUE false ENABLE_NON_DESTRUCTIVE_CALIB false FIX_READ_LATENCY 8 USE_USER_RDIMM_VALUE false ENABLE_DELAY_CHAIN_WRITE false TRACKING_ERROR_TEST false TRACKING_WATCH_TEST false MARGIN_VARIATION_TEST false AC_ROM_USER_ADD_0 0_0000_0000_0000 AC_ROM_USER_ADD_1 0_0000_0000_1000 TREFI 35100 REFRESH_INTERVAL 15000 ENABLE_NON_DES_CAL_TEST false TRFC 350 ENABLE_NON_DES_CAL false EXTRA_SETTINGS MEM_DEVICE MISSING_MODEL FORCE_SYNTHESIS_LANGUAGE NUM_SUBGROUP_PER_READ_DQS 1 QVLD_EXTRA_FLOP_STAGES 1 QVLD_WR_ADDRESS_OFFSET 5 MAX_WRITE_LATENCY_COUNT_WIDTH 4 NUM_WRITE_PATH_FLOP_STAGES 1 NUM_AC_FR_CYCLE_SHIFTS 0 FORCED_NUM_WRITE_FR_CYCLE_SHIFTS 0 NUM_WRITE_FR_CYCLE_SHIFTS 0 PERFORM_READ_AFTER_WRITE_CALIBRATION true SEQ_BURST_COUNT_WIDTH 2 VCALIB_COUNT_WIDTH 2 PLL_PHASE_COUNTER_WIDTH 4 DQS_DELAY_CHAIN_PHASE_SETTING 0 DQS_PHASE_SHIFT 0 DELAYED_CLOCK_PHASE_SETTING 2 IO_DQS_IN_RESERVE 4 IO_DQS_OUT_RESERVE 4 IO_DQ_OUT_RESERVE 0 IO_DM_OUT_RESERVE 0 IO_DQS_EN_DELAY_OFFSET 0 IO_DQS_EN_PHASE_MAX 7 IO_DQDQS_OUT_PHASE_MAX 0 IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS false MEM_CLK_NS 3.003 MEM_CLK_PS 3003.0 CALIB_LFIFO_OFFSET 8 CALIB_VFIFO_OFFSET 6 DELAY_PER_OPA_TAP 375 DELAY_PER_DCHAIN_TAP 25 DELAY_PER_DQS_EN_DCHAIN_TAP 25 DQS_EN_DELAY_MAX 31 DQS_IN_DELAY_MAX 31 IO_IN_DELAY_MAX 31 IO_OUT1_DELAY_MAX 31 IO_OUT2_DELAY_MAX 0 IO_STANDARD SSTL-15 VFIFO_AS_SHIFT_REG true SEQUENCER_TYPE NIOS NIOS_HEX_FILE_LOCATION ../ ADVERTIZE_SEQUENCER_SW_BUILD_FILES false NEGATIVE_WRITE_CK_PHASE true MEM_T_WL 6 MEM_T_RL 7 PHY_CLKBUF false USE_LDC_AS_LOW_SKEW_CLOCK false USE_LDC_FOR_ADDR_CMD false ENABLE_LDC_MEM_CK_ADJUSTMENT false MEM_CK_LDC_ADJUSTMENT_THRESHOLD 0 LDC_FOR_ADDR_CMD_MEM_CK_CPS_INVERT true LDC_FOR_ADDR_CMD_MEM_CK_CPS_PHASE 0 FORCED_NON_LDC_ADDR_CMD_MEM_CK_INVERT false NON_LDC_ADDR_CMD_MEM_CK_INVERT false REGISTER_C2P false EARLY_ADDR_CMD_CLK_TRANSFER true MAX10_RTL_SEQ false PHY_ONLY false SEQ_MODE 0 ADVANCED_CK_PHASES false COMMAND_PHASE 0.0 MEM_CK_PHASE 0.0 P2C_READ_CLOCK_ADD_PHASE 0.0 C2P_WRITE_CLOCK_ADD_PHASE 0.0 ACV_PHY_CLK_ADD_FR_PHASE 0.0 MEM_VOLTAGE 1.5V DDR3 PLL_LOCATION Top_Bottom SKIP_MEM_INIT true READ_DQ_DQS_CLOCK_SOURCE INVERTED_DQS_BUS DQ_INPUT_REG_USE_CLKN false DQS_DQSN_MODE DIFFERENTIAL AFI_DEBUG_INFO_WIDTH 32 CALIBRATION_MODE Skip NIOS_ROM_DATA_WIDTH 32 NIOS_ROM_ADDRESS_WIDTH 13 READ_FIFO_SIZE 8 PHY_CSR_ENABLED false PHY_CSR_CONNECTION INTERNAL_JTAG USER_DEBUG_LEVEL 0 TIMING_BOARD_DERATE_METHOD AUTO TIMING_BOARD_CK_CKN_SLEW_RATE 2.0 TIMING_BOARD_AC_SLEW_RATE 1.0 TIMING_BOARD_DQS_DQSN_SLEW_RATE 2.0 TIMING_BOARD_DQ_SLEW_RATE 1.0 TIMING_BOARD_CK_CKN_SLEW_RATE_APPLIED 2.0 TIMING_BOARD_AC_SLEW_RATE_APPLIED 1.0 TIMING_BOARD_DQS_DQSN_SLEW_RATE_APPLIED 2.0 TIMING_BOARD_DQ_SLEW_RATE_APPLIED 1.0 TIMING_BOARD_TIS 0.0 TIMING_BOARD_TIH 0.0 TIMING_BOARD_TDS 0.0 TIMING_BOARD_TDH 0.0 TIMING_BOARD_TIS_APPLIED 0.335 TIMING_BOARD_TIH_APPLIED 0.23 TIMING_BOARD_TDS_APPLIED 0.205 TIMING_BOARD_TDH_APPLIED 0.155 TIMING_BOARD_ISI_METHOD AUTO TIMING_BOARD_AC_EYE_REDUCTION_SU 0.0 TIMING_BOARD_AC_EYE_REDUCTION_H 0.0 TIMING_BOARD_DQ_EYE_REDUCTION 0.0 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME 0.0 TIMING_BOARD_READ_DQ_EYE_REDUCTION 0.0 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME 0.0 TIMING_BOARD_AC_EYE_REDUCTION_SU_APPLIED 0.0 TIMING_BOARD_AC_EYE_REDUCTION_H_APPLIED 0.0 TIMING_BOARD_DQ_EYE_REDUCTION_APPLIED 0.0 TIMING_BOARD_DELTA_DQS_ARRIVAL_TIME_APPLIED 0.0 TIMING_BOARD_READ_DQ_EYE_REDUCTION_APPLIED 0.0 TIMING_BOARD_DELTA_READ_DQS_ARRIVAL_TIME_APPLIED 0.0 PACKAGE_DESKEW false AC_PACKAGE_DESKEW false TIMING_BOARD_MAX_CK_DELAY 0.6 TIMING_BOARD_MAX_DQS_DELAY 0.6 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN -0.01 TIMING_BOARD_SKEW_CKDQS_DIMM_MIN_APPLIED -0.01 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX 0.01 TIMING_BOARD_SKEW_CKDQS_DIMM_MAX_APPLIED 0.01 TIMING_BOARD_SKEW_BETWEEN_DIMMS 0.05 TIMING_BOARD_SKEW_BETWEEN_DIMMS_APPLIED 0.0 TIMING_BOARD_SKEW_WITHIN_DQS 0.02 TIMING_BOARD_SKEW_BETWEEN_DQS 0.02 TIMING_BOARD_DQ_TO_DQS_SKEW 0.0 TIMING_BOARD_AC_SKEW 0.02 TIMING_BOARD_AC_TO_CK_SKEW 0.0 ENABLE_EXPORT_SEQ_DEBUG_BRIDGE false CORE_DEBUG_CONNECTION EXPORT ADD_EXTERNAL_SEQ_DEBUG_NIOS false ED_EXPORT_SEQ_DEBUG false ADD_EFFICIENCY_MONITOR false ENABLE_ABS_RAM_MEM_INIT false ENABLE_ABS_RAM_INTERNAL false ENABLE_ABSTRACT_RAM false ABS_RAM_MEM_INIT_FILENAME meminit DLL_DELAY_CTRL_WIDTH 7 DLL_OFFSET_CTRL_WIDTH 6 DELAY_BUFFER_MODE HIGH DELAY_CHAIN_LENGTH 8 DLL_SHARING_MODE None NUM_DLL_SHARING_INTERFACES 1 OCT_TERM_CONTROL_WIDTH 16 OCT_SHARING_MODE None NUM_OCT_SHARING_INTERFACES 1 AUTO_DEVICE 5CEFA5F23C8 AUTO_DEVICE_SPEEDGRADE 8 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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mm_clock_crossing_bridge_0

altera_avalon_mm_clock_crossing_bridge v23.1

Parameters DATA_WIDTH 32 SYMBOL_WIDTH 8 ADDRESS_WIDTH 10 SYSINFO_ADDR_WIDTH 29 USE_AUTO_ADDRESS_WIDTH 1 AUTO_ADDRESS_WIDTH 27 HDL_ADDR_WIDTH 27 ADDRESS_UNITS WORDS BURSTCOUNT_WIDTH 1 MAX_BURST_SIZE 1 COMMAND_FIFO_DEPTH 4 RESPONSE_FIFO_DEPTH 4 MASTER_SYNC_DEPTH 2 SLAVE_SYNC_DEPTH 2 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)

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reset_bridge_0

altera_reset_bridge v23.1

Parameters ACTIVE_LOW_RESET 1 SYNCHRONOUS_EDGES deassert NUM_RESET_OUTPUTS 1 USE_RESET_REQUEST 0 AUTO_CLK_CLOCK_RATE 166666666 deviceFamily UNKNOWN generateLegacySim false

  

Software Assignments (none)