# Copyright (C) 1991-2006 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		usbHostSlaveAvalonWrap_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY Cyclone
set_global_assignment -name DEVICE EP1C4F400C7
set_global_assignment -name TOP_LEVEL_ENTITY usbHostSlaveAvalonWrap
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "19:38:48  OCTOBER 06, 2006"
set_global_assignment -name LAST_QUARTUS_VERSION "6.0 SP1"
set_global_assignment -name VERILOG_FILE src/writeUSBWireData.v
set_global_assignment -name VERILOG_FILE src/directcontrol.v
set_global_assignment -name VERILOG_FILE src/dpMem_dc.v
set_global_assignment -name VERILOG_FILE src/endpMux.v
set_global_assignment -name VERILOG_FILE src/fifoMux.v
set_global_assignment -name VERILOG_FILE src/fifoRTL.v
set_global_assignment -name VERILOG_FILE src/getpacket.v
set_global_assignment -name VERILOG_FILE src/hctxportarbiter.v
set_global_assignment -name VERILOG_FILE src/hostcontroller.v
set_global_assignment -name VERILOG_FILE src/hostSlaveMux.v
set_global_assignment -name VERILOG_FILE src/hostSlaveMuxBI.v
set_global_assignment -name VERILOG_FILE src/lineControlUpdate.v
set_global_assignment -name VERILOG_FILE src/processRxBit.v
set_global_assignment -name VERILOG_FILE src/processRxByte.v
set_global_assignment -name VERILOG_FILE src/processTxByte.v
set_global_assignment -name VERILOG_FILE src/readUSBWireData.v
set_global_assignment -name VERILOG_FILE src/RxFifo.v
set_global_assignment -name VERILOG_FILE src/RxFifoBI.v
set_global_assignment -name VERILOG_FILE src/rxStatusMonitor.v
set_global_assignment -name VERILOG_FILE src/sctxportarbiter.v
set_global_assignment -name VERILOG_FILE src/sendpacket.v
set_global_assignment -name VERILOG_FILE src/sendpacketarbiter.v
set_global_assignment -name VERILOG_FILE src/sendpacketcheckpreamble.v
set_global_assignment -name VERILOG_FILE src/siereceiver.v
set_global_assignment -name VERILOG_FILE src/SIETransmitter.v
set_global_assignment -name VERILOG_FILE src/slavecontroller.v
set_global_assignment -name VERILOG_FILE src/slaveDirectcontrol.v
set_global_assignment -name VERILOG_FILE src/slaveGetpacket.v
set_global_assignment -name VERILOG_FILE src/slaveRxStatusMonitor.v
set_global_assignment -name VERILOG_FILE src/slaveSendpacket.v
set_global_assignment -name VERILOG_FILE src/sofcontroller.v
set_global_assignment -name VERILOG_FILE src/softransmit.v
set_global_assignment -name VERILOG_FILE src/speedCtrlMux.v
set_global_assignment -name VERILOG_FILE src/timescale.v
set_global_assignment -name VERILOG_FILE src/TxFifo.v
set_global_assignment -name VERILOG_FILE src/TxFifoBI.v
set_global_assignment -name VERILOG_FILE src/updateCRC5.v
set_global_assignment -name VERILOG_FILE src/updateCRC16.v
set_global_assignment -name VERILOG_FILE src/usbConstants_h.v
set_global_assignment -name VERILOG_FILE src/usbHostControl.v
set_global_assignment -name VERILOG_FILE src/usbHostControl_h.v
set_global_assignment -name VERILOG_FILE src/USBHostControlBI.v
set_global_assignment -name VERILOG_FILE src/usbHostSlave.v
set_global_assignment -name VERILOG_FILE src/usbHostSlave_h.v
set_global_assignment -name VERILOG_FILE src/usbHostSlaveAvalonWrap.v
set_global_assignment -name VERILOG_FILE src/usbSerialInterfaceEngine.v
set_global_assignment -name VERILOG_FILE src/usbSerialInterfaceEngine_h.v
set_global_assignment -name VERILOG_FILE src/usbSlaveControl.v
set_global_assignment -name VERILOG_FILE src/usbSlaveControl_h.v
set_global_assignment -name VERILOG_FILE src/USBSlaveControlBI.v
set_global_assignment -name VERILOG_FILE src/usbTxWireArbiter.v
set_global_assignment -name VERILOG_FILE src/wishBoneBI.v
set_global_assignment -name VERILOG_FILE src/wishBoneBus_h.v